Selectively automating non-critical aspects of custom IC design allows engineers to focus on precision-crafting their designs. Cadence circuit design solutions enable fast and accurate entry of design concepts, which includes managing design intent in a way that flows naturally in the schematic. Using this advanced, parasitic-aware environment, you can abstract and visualize the many interdependencies of an analog, RF, or mixed-signal design to understand and determine their effects on circuit performance.
Our circuit design flow is centered around Cadence® Virtuoso® Schematic Editor and the Cadence Virtuoso ADE Product Suite. These tools work together to provide the basis of your design and all its needed testing. These tools are also well integrated with a variety of Cadence simulation and physical implementation tools, allowing for seamless information sharing. As a result, you benefit from continuous verification throughout the entire analog, RF, or mixed-signal design cycle, along with the highest level of confidence that your design was done right the first time.
Virtuoso Schematic Editor delivers
The necessary tools and accelerators to render a fully hierarchical, multi-page schematic for the most complex design
An editor that assists in the creation of IEEE 1801 low-power representations of analog devices models for modeling and testing low-power designs with the analog circuit environment
Design constraints that help you maintain and preserve design intent by providing electronically tracked information about special needs the circuit may have in terms of construction
Virtuoso ADE Product Suite delivers
A reduced learning curve with a simulator-independent environment
A combination of a GUI-based and script-driven environment for maximum efficiency, depending on where you are in the design process
Accelerated debug processes using a variety of built-in analog analysis tools to explore the corners and statistical variances of the design to find errors before they go into production
Facilitated design correction due to physical implementation via an easy comparison of pre- and post-parasitic extracted designs
Quick detection of circuit problems via a clear waveform visualization cockpit with an extensive waveform calculator