Power-optimization techniques are creating new complexities in the physical and functional behavior of electronic designs. An integral piece of a functional verification plan, Cadence’s power-aware verification methodology can help verify power optimization without impacting design intent, minimizing late-cycle errors and debugging cycles. After all, simulating without power intent is like simulation with some RTL code black boxed.

The methodology brings together power-aware elaboration with formal analysis and simulation. With power-aware elaboration, all of the blocks as well as the power management features in your design are in place, so you can verify your design with power intent. Power intent introduces power/ground nets, voltage levels, power switches, isolation cells, and state retention registers. Any verification technology—simulation, emulation, prototyping, or formal—can be applied on a power-aware elaboration of the design.

By investing upfront time and effort to learn and apply the tools in this flow, you can avoid design problems that, later in the cycle, will take much longer to find and fix. Figure 1 outlines the key steps of our power-aware verification methodology.

Steps in the Power-Aware Flow

Step 0: Write and scrub the CPF/UPF power intent

• For pre-simulation power-intent screening, use Cadence^® Conformal^® Equivalence Checker, which lets you formally verify and debug multi-million-gate designs without test vectors
• Ensure power intent is verification-ready with Cadence JasperGold^® Low-Power Verification App, which exhaustively verifies design functionality with static and dynamic power optimization techniques

Step 1: Create a power-aware, power feature verification plan

• Organize your tests by power feature and verification method; formalize the planning and management process with Cadence vManager^™ Metric-Driven Signoff Platform
• Distinguish between block and SoC level, or both, and test as much as you can at the block level
• Choose a platform for verifying each entry; cover as much of your test plan as possible with static/formal engines to avoid risk of incomplete dynamic test coverage

Step 2: Execute formal aspects of verification plan with JasperGold Low Power Verification App, which automatically creates power-aware RTL for:

• Power-aware property checking
• Power-optimization using SEC
• Checking for new X sources introduced by power intent
• Exhaustive verification of power-up and power-down sequencing

Step 3: Create dynamic tests for balance of verification plan

• Transform all verification tests to be power aware
• Generate tests and checks that are portable across verification engines
• Use Cadence Perspec^™ System Verifier as a portable stimulus generator for verification of power management features

Step 4: Execute dynamic tests on assigned engine. Use the best engine for each type of test. For example:

• Cadence Xcelium^™ Parallel Logic Simulation is used to verify that power intent as described in the Common Power Format or Unified Power Format files is correctly implemented, including:
  • Logical netlist power domain reset, initialization, and control behavior
  • Physical netlists containing post place-and-route buffering and clock networks
  • IP interfaces and power domain interactions at the SoC level
  • Test structures such as BIST and scan chains that do not have an RTL equivalent
    
• The Cadence Palladium Z1 works well for long, or “deep,” tests like hardware/software integration and software power state control
  
• The Cadence Protium^™ S1 FPGA-Based Prototyping Platform is a valuable tool for software developers to verify that power control and application software work together as expected
  

Step 5: Merge metrics coverage reporting, using the vManager Metric-Driven Signoff Platform to view, report, and manage coverage

Step 6: Normal cycle of debug/fix/regress. Repeat all tests if there are power-intent changes. Automate the regression trigger based on power-intent changes by design and implementation teams