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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
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      • Industries
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        • Hyperscale Computing
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        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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Power-Aware Verification Methodology

Minimize late-cycle errors and debugging cycles

Power-Aware Verification Methodology

Minimize late-cycle errors and debugging cycles

  • Low-Power Solution
  • Power-Aware Verification Methodology
  • Power-Aware Implementation

Key Benefits

  • Verify your power-optimized design 
  • Ensure that power management features don’t interfere with design intent
  • Completely verify your SoC with fully integrated flow

Power-optimization techniques are creating new complexities in the physical and functional behavior of electronic designs. An integral piece of a functional verification plan, Cadence’s power-aware verification methodology can help verify power optimization without impacting design intent, minimizing late-cycle errors and debugging cycles. After all, simulating without power intent is like simulation with some RTL code black boxed.

The methodology brings together power-aware elaboration with formal analysis and simulation. With power-aware elaboration, all of the blocks as well as the power management features in your design are in place, so you can verify your design with power intent. Power intent introduces power/ground nets, voltage levels, power switches, isolation cells, and state retention registers. Any verification technology—simulation, emulation, prototyping, or formal—can be applied on a power-aware elaboration of the design.

By investing upfront time and effort to learn and apply the tools in this flow, you can avoid design problems that, later in the cycle, will take much longer to find and fix. Figure 1 outlines the key steps of our power-aware verification methodology.

Low-Power Solution Power Aware Verification Methodology
Abstract view of Cadence power-aware verification methodology. This basic flow applies at any stage of design, from RTL through signoff.

Steps in the Power-Aware Flow

Step 0: Write and scrub the CPF/UPF power intent

  • For pre-simulation power-intent screening, use Cadence® Conformal® Equivalence Checker, which lets you formally verify and debug multi-million-gate designs without test vectors
  • Ensure power intent is verification-ready with Cadence JasperGold® Low-Power Verification App, which exhaustively verifies design functionality with static and dynamic power optimization techniques

Step 1: Create a power-aware, power feature verification plan

  • Organize your tests by power feature and verification method; formalize the planning and management process with Cadence vManager™ Metric-Driven Signoff Platform
  • Distinguish between block and SoC level, or both, and test as much as you can at the block level
  • Choose a platform for verifying each entry; cover as much of your test plan as possible with static/formal engines to avoid risk of incomplete dynamic test coverage

Step 2: Execute formal aspects of verification plan with JasperGold Low Power Verification App, which automatically creates power-aware RTL for:

  • Power-aware property checking
  • Power-optimization using SEC
  • Checking for new X sources introduced by power intent
  • Exhaustive verification of power-up and power-down sequencing

Step 3: Create dynamic tests for balance of verification plan

  • Transform all verification tests to be power aware
  • Generate tests and checks that are portable across verification engines
  • Use Cadence Perspec™ System Verifier as a portable stimulus generator for verification of power management features

Step 4: Execute dynamic tests on assigned engine. Use the best engine for each type of test. For example:

  • Cadence Xcelium™ Parallel Logic Simulation is used to verify that power intent as described in the Common Power Format or Unified Power Format files is correctly implemented, including:
    • Logical netlist power domain reset, initialization, and control behavior
    • Physical netlists containing post place-and-route buffering and clock networks
    • IP interfaces and power domain interactions at the SoC level
    • Test structures such as BIST and scan chains that do not have an RTL equivalent
  • The Cadence Palladium Z1 works well for long, or “deep,” tests like hardware/software integration and software power state control
  • The Cadence Protium™ S1 FPGA-Based Prototyping Platform is a valuable tool for software developers to verify that power control and application software work together as expected

Step 5: Merge metrics coverage reporting, using the vManager Metric-Driven Signoff Platform to view, report, and manage coverage

Step 6: Normal cycle of debug/fix/regress. Repeat all tests if there are power-intent changes. Automate the regression trigger based on power-intent changes by design and implementation teams

  • Related Products

    • Cadence Verification
    • Conformal Low Power
    • Jasper Low-Power Verification App
    • vManager Verification Management
    • Perspec System Verifier
    • Xcelium Logic Simulator
    • Palladium Z1 Enterprise Emulation Platform
    • Protium S1 Desktop Prototyping Platform
    • Palladium Dynamic Power Analysis
    • Indago Debug Analyzer
    • Joules RTL Power Solution
    • Voltus IC Power Integrity Solution
News ReleasesVIEW ALL
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  • Cadence Achieves PCIe 5.0 Specification Compliance for PHY and Controller IP in TSMC Advanced Technologies 06/21/2022

  • Cadence Announces $100 Million Accelerated Share Repurchase Agreement 06/21/2022

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