Unleash the Full Potential of Massive Design Data by Tapping into Hidden Data Insights

Verification and implementation of large and complex systems on chip (SoCs) generate vast amounts of data that is not always exploited to its full potential. Most of the workflow and design data created is difficult to discern easily, so is unavailable for designers to consume. The Cadence Joint Enterprise Data and AI (JedAI) Platform is able to harness this rich lode of EDA data in an open, artificial intelligence (AI)-driven, large-scale data analytics environment, allowing engineering teams to visualize the data, uncover hidden data trends, and automatically generate design improvement strategies leading to improved design performance and engineering productivity.

With the Cadence JedAI Platform, Cadence unifies its computational software innovations in data and AI across Verisium AI-Driven Verification, Cadence Cerebrus Intelligent Chip Explorer’s AI-driven implementation, and Optimality Intelligent System Explorer’s AI-driven system analysis, enabling a generational shift from single-run, single-engine algorithms in electronic design automation (EDA) to leveraging big data and AI to optimize multiple runs of multiple engines across an entire SoC design and verification flow.

Key Benefits

Scalability

Enables vertical knowledge transfer throughout the design cycle and parallel transfer of information across multiple designs as well as carrying it forward to future designs

Actionable Data

AI-driven data analytics provide a holistic view of EDA data and unravel interesting design trends leading to faster design debug and improved performance

Productivity Multiplier

Eliminates manual data triaging, autonomously optimizing a vast amount of EDA data and enabling efficient design closure

Features

  • Leverages latest advancements in data science and machine learning (ML) to provide a secure, highly distributed, cloud-enabled infrastructure to store and optimize vast amounts of design data, workflow data, and workload data.
  • Allows ingestion of a wide variety of data sources in a simple, scalable way using dedicated Cadence data connectors. Also provides general-purpose open data connectors so designers can easily import third-party data as needed.
  • Deploys big data analytics and ML capabilities to make insightful observations of the EDA data, unravels the untapped design trends, and produces designer-friendly visualizations and dashboards thereof to efficiently design complex SoCs.
  • Presents the data mined into an actionable and consumable format by generating clues and clear solutions to debug and fix design issues, enriching the designer experience and accelerating design closure.