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DESIGN EXCELLENCE

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CADENCE CLOUD

Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

  • Logic Equivalence Checking
  • Innovus Implementation and Floorplanning
  • Functional ECO
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  • Achieve best PPA with the next-generation Digital Full Flow solution Learn More
  • Address digital implementation challenges with machine learning Watch Now

Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

  • Circuit Design
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  • Solve analog simulation challenges in complex designs Watch Now
  • See how the Virtuoso Design Platform addresses advanced custom IC and system design challenges Watch Now

System Design and Verification

Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

  • Debug Analysis
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  • Planning and Management
  • Simulation
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  • Verification IP
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  • Flows
  • Prototype your embedded software development Watch Now
  • Learn how early firmware development enabled first silicon success at Toshiba Memory Watch Now

IP

An open IP platform for you to customize your app-driven SoC design.

  • Interface IP
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  • Verification IP
  • Solve the challenges of long-reach signaling with Cadence 112G SerDes IP Watch Now
  • Meeting the needs of 5G communication with Tensilica® ConnX B20 DSP IP Download Now

IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

  • Cross-Platform Co-Design and Analysis
  • IC Package Design
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
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  • Cadence Design Solutions certified for TSMC SoIC advanced 3D chip stacking technology Learn More
  • Four reasons to avoid multi-layer flip-chip pin padstacks Learn More

System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

  • See how to improve electrical-thermal co-simulation with the Celsius™ Thermal Solver Watch Now
  • Get true 3D system analysis with faster speeds, more capacity, and integration Watch Now
  • Electromagnetic Solutions
  • RF / Microwave Design
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  • System Analysis Resources Hub

Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

  • Design Authoring
  • PCB Layout
  • Library and Design Data Management
  • Analog/Mixed-Signal Simulation
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • What's New in Allegro
  • What's New in Sigrity
  • RF / Microwave Design
  • Flows
  • Advanced PCB Design & Analysis Blog
  • Watch how to easily tackle complex and cutting edge designs. Learn More
  • Learn why signal integrity analysis needs to be power-aware Watch Now
  • Augmented Reality Lab Tools

AI / Machine Learning

AI IP Portfolio

INDUSTRIES

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TECHNOLOGIES

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See how our customers create innovative products with Cadence Explore Now

SUPPORT

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TRAINING

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Learn how Intelligent System Design™ powers future technologies Learn More
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View all Products
  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
  • 솔루션
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • 기술지원 및 교육
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
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      • MEDIA CENTER
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      • CULTURE AND CAREERS
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      • CORPORATE
        • About Us
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FPGA Development

Comprehensive Flow for Complex FPGAs

Key Benefits

  • From system design, to verification, to board implementation flow
  • Scalable verification methodology
  • Native integration into FPGA vendor flows
  • Complete set of tools and methodologies for DO-254 compliance
  • Methodology and tool support for DO-254 verification requirements traceability

Due to the ever-increasing costs of development and manufacturing of custom IC devices as well as the flexibility that FPGAs provide, many system houses use FPGA devices not just for prototype or early availability runs, but for the entire life of the product. The result is the number of designs that are implemented in FPGAs is growing, and the complexity of those designs is increasing, requiring more powerful EDA tools for design, up-front verification, debug, and implementation.

Cadence offers a variety of tools and methodologies that enable users to develop their FPGA designs quickly and effectively to improve quality and time to FPGA signoff. Our tools and our FPGA vendor relationships help users avoid long programming and field testing cycles.

Let us help you:

  • Track and sign off top-level requirements through all transformations for safety
  • Use techniques and methodologies to improve design productivity
  • Improve design creation and reuse of code
  • Implement system synthesis that feeds FPGA synthesis tools
  • Integrate coverage between formal and simulation increase coverage

Our portfolio includes:

  • Ability to track requirements through signoff for high-reliability, safety-critical, or any complex FPGA design projects with the vManager™ Metric-Driven Signoff Platform
  • Automatic creation of high-quality register-level (RTL) design implementations for FPGA designs with Stratus™ High-Level Synthesis
  • Broad memory and protocol support with Cadence® design IP, memory IP, and verification IP (VIP)
  • Formal verification through JasperGold® Apps to find more bugs in less time and earlier in the design process
  • High-performance simulation with comprehensive VHDL, SystemVerilog, and other language support with the Xcelium™ Parallel Logic Simulator
  • Rapid prototyping with debug and emulation congruence with Protium™ S1 FPGA-Based Prototyping Platform
  • Fast system debug, acceleration, and emulation with Palladium® Z1 Enterprise Emulation Platform
  • Rapid generation of system stimulus with the Perspec™ System Verifier
  • Automatic pin assignment synthesis for rapid PCB development with the Allegro® FPGA System Planner

 

FPGA Flow
  • Related Products

    • Allegro FPGA System Planner
    • JasperGold Formal Verification Platform (Apps)
    • Palladium Z1 Enterprise Emulation System
    • Perspec System Verifier
    • Protium S1 Desktop Prototyping Platform
    • Stratus High-Level Synthesis
    • Verification IP
    • vManager Verification Management
    • Xcelium Logic Simulator
Resource Library

Video (10)

  • New Cadence Products Expand the Verification Suite: Xcelium Parallel Simulator and Protium S1 Platform
  • Faster Routing by Optimizing FPGA Pin Assignments
  • Protium S1 used to prototype a pedestrian detection application.
  • Xilinx - Industry Leading Solutions for FPGA-based Prototyping
  • Faster HW/SW Debug, Embedded Software Development and System Validation
  • Accelerating design-in of Xilinx FPGAs while optimizing PCB layout for cost and performance
  • Accelerating design-in of Altera FPGAs while optimizing PCB layout for cost and performance
  • Hitachi: Faster Bring Up with Protium Platform
  • FPGA board design: Introduction to Cadence FPGA System Planner
  • The Best of Both Worlds – Combining Virtual and FPGA-based Prototypes

Technical Brief (1)

  • ASIC Prototyping Simplified Technical Paper

Datasheet (7)

  • Protium S1 FPGA-Based Prototyping Platform
  • Perspec System Verifier Datasheet
  • Protium S1 Single-FPGA Board Datasheet
  • vManager Metric-Driven Signoff Platform Datasheet
  • Palladium Z1 Enterprise Emulation Platform Datasheet
  • Protium FPGA-Based Prototyping Platform Datasheet
  • Allegro FPGA System Planner Datasheet
VIEW ALL
News ReleasesVIEW ALL
  • Cadence Launches Protium X1, the First Scalable, Data Center-Optimized Enterprise Prototyping System for Early Software Development 05/28/2019

  • NVIDIA Deploys the New Cadence Protium X1 Platform to Accelerate Software Development of Large-Capacity GPUs 05/28/2019

  • Hiroshima University Research Team Accelerates the Development of a Computer-Aided Medical Diagnosis System with Cadence Tensilica Vision P6 DSP Core and Protium S1 FPGA-Based Prototyping Platform 10/11/2017

  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard 10/11/2017

  • Amlogic Reduces HW/SW Integration Time for Multimedia SoCs by Two Months Using the Cadence Protium S1 FPGA-Based Prototyping Platform 04/26/2017

Blogs VIEW ALL

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