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Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
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From staying up-to-date on the latest standards to managing all of the associated data, complying with functional safety requirements has traditionally been a time-consuming, manual effort. Cadence is transforming this process by automating fault injection and result analysis for intellectual property (IP), system-on-chip (SoC), and system designs.
Checkers, which monitor the systems and trigger error recovery features when necessary
Redundancy, which provides continuous function in the event of errors
For their part, safety engineers must implement requirements tracing from the system to components, and ensure that their development flow aligns with tool confidence level (TCL). Functional verification should take place at all levels of abstraction and for all system elements. Safety verification, which measures response of systems to undesired/unplanned events, is another critical step. Finally, to be in full compliance, safety engineers must record and report on all functional safety measures.
Built on Proven Incisive Platform
Fulfilling the traceability, safety verification, and TCL requirements of ISO 26262, Cadence’s functional safety solution includes Incisive Functional Safety Simulator and a functional safety analysis capability in the Cadence vManager™ Metric-Driven Signoff Platform.
Incisive Functional Safety Simulator delivers:
Seamless reuse of functional and mixed-signal verification environments to accelerate the time to develop safety verification
Fault identification during elaboration
Reuse of the existing functional verification environment (with support for SystemVerilog, Universal Verification Methodology (UVM), and e)
Simulation of the unaltered design under test (DUT)
Support for multiple fault types, including single event upset (SEU), stuck-at-0/stuck-at-1, and single event transient
The functional safety analysis capability in the vManager platform:
Automatically generates a safety verification plan from the fault dictionary created by the simulator. The vManager platform can then track millions of detected, partially detected, and undetected faults introduced into simulation to verify the safety systems in a design.
Highlights potential and undetected fault runs for further debugging
Cadence will continue to expand its functional safety solution to encompass additional hardware, software, and IP components.
In this Whiteboard Wednesdays video, Charles Qi talks about automotive functional safety and reliability standards and their importance to the automobile industry and to IP and software developers.
