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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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  • Achieve best PPA with the next-generation Digital Full Flow solution Learn More
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Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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  • Solve analog simulation challenges in complex designs Watch Now
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System Design and Verification

Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

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IP

An open IP platform for you to customize your app-driven SoC design.

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  • Solve the challenges of long-reach signaling with Cadence 112G SerDes IP Watch Now
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IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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  • Cadence Design Solutions certified for TSMC SoIC advanced 3D chip stacking technology Learn More
  • Four reasons to avoid multi-layer flip-chip pin padstacks Learn More

System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

  • See how to improve electrical-thermal co-simulation with the Celsius™ Thermal Solver Watch Now
  • Get true 3D system analysis with faster speeds, more capacity, and integration Watch Now
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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

  • Design Authoring
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  • Watch how to easily tackle complex and cutting edge designs. Learn More
  • Learn why signal integrity analysis needs to be power-aware Watch Now
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AI / Machine Learning

AI IP Portfolio

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View all Products
  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
  • 솔루션
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • 기술지원 및 교육
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        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
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        • Tensilica Processor IP
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Functional Safety

Reduce your ISO 26262 compliance effort by 50%

Automotive Electronics Overview
  • Automotive Solution
  • Advanced Driver Assistance System
  • Automotive Ethernet
  • Infotainment
  • Electronic Control Unit
  • Functional Safety
  • Automotive SoC Design

From staying up-to-date on the latest standards to managing all of the associated data, complying with functional safety requirements has traditionally been a time-consuming, manual effort. Cadence is transforming this process by automating fault injection and result analysis for intellectual property (IP), system-on-chip (SoC), and system designs.

ASK US A QUESTION

Safety Analysis to Measure Continuous Operation

Meeting functional safety requirements calls for:

  • Safety mechanisms, which monitor the systems and trigger error recovery features when necessary
  • Redundancy, which provides continuous function in the event of errors

For their part, safety engineers must implement requirements tracing from the system to components, and ensure that their development flow aligns with tool confidence level (TCL). Functional verification should take place at all levels of abstraction and for all system elements. Safety verification, which measures response of systems to undesired/unplanned events, is another critical step. Finally, to be in full compliance, safety engineers must record and report on all functional safety measures.

Cadence Safety Verification Solution

Fulfilling the traceability, safety verification, and TCL requirements of ISO 26262, Cadence’s functional safety solution includes Incisive Functional Safety Simulator and a functional safety analysis capability in the Cadence vManager™ Metric-Driven Signoff Platform.

Incisive Functional Safety Simulator delivers:

  • Seamless reuse of functional and mixed-signal verification environments to accelerate the time to develop safety verification
  • Fault identification during elaboration
  • Reuse of the existing functional verification environment (with support for SystemVerilog, Universal Verification Methodology (UVM), and e)
  • Simulation of the unaltered design under test (DUT)
  • Support for multiple fault types, including single event upset (SEU), stuck-at-0/stuck-at-1, and single event transient

The functional safety analysis capability in the vManager platform:

  • Automatically generates a safety verification plan from the fault dictionary created by the simulator. The vManager platform can then track millions of detected, partially detected, and undetected faults introduced into simulation to verify the safety systems in a design.
  • Highlights potential and undetected fault runs for further debugging

Cadence will continue to expand its functional safety solution to encompass additional hardware, software, and IP components.

  • Related Products

    • vManager Verification Management
    • Incisive Functional Safety Simulator
    • Cadence Verification Suite
  • Automotive White Papers

    • Functional Safety Methodologies for Automotive Applications White Paper
    • Automotive Functional Safety Using LBIST and Other Detection Methods
    • Improve Reliability and Redundancy of Automotive Ethernet Through Open Standards
    • Meeting Functional Safety Requirements Efficiently Via Electronic Design Tools and Techniques White Paper
    • Improving Test Coverage and Eliminating Test Ecapes Using Analog Defect Analysis White Paper
    • Analog Reliability Analysis for Mission-Critical Applications White Paper

In this Whiteboard Wednesdays video we talk about automotive functional safety and reliability standards and their importance to the automobile industry and to IP and software developers.

Videos

Functional Safety Flow for ISO 26262 ASIL-C of D Analysis

Is Your Design Functionally Safe?

The Truth about Designing for Automotive Functional Safety

Simplifying Fault Injection Simulations for Functional Safety Verification

Automotive Functional Safety and Reliability Requirements

Understanding ISO 26262 Implications for Automotive Design Teams

News ReleasesVIEW ALL
  • Cadence Tensilica Product Development Process and Software Products Certified for ISO 26262 ASIL D Compliance for Automotive Applications 02/28/2019

  • Cadence Automotive Solution for Safety Verification Used by ROHM to Achieve ISO 26262 ASIL D Certification 07/12/2018

  • Cadence Automotive Solution for Safety Verification Used by ROHM to Achieve ISO 26262 ASIL D Certification 07/12/2018

  • Cadence Debuts Industry’s First Analog IC Design-for-Reliability Solution 05/08/2018

  • Cadence Boosts Vision and AI Performance with New Tensilica Vision Q6 DSP IP 04/11/2018

Blogs VIEW ALL
Resource Library

Press Releases (6)

  • Cadence Tensilica Product Development Process and Software Products Certified for ISO 26262 ASIL D Compliance for Automotive Applications
  • Cadence Automotive Solution for Safety Verification Used by ROHM to Achieve ISO 26262 ASIL D Certification
  • Cadence Functional Safety Verification Solution Adopted for ISO 26262-Compliant Automotive IC Development Flow at ROHM
  • Cadence offers broadest tool support for ISO 26262
  • Cadence Introduces Automotive Functional Safety Verification Solution, Reducing ISO 26262 Compliance Preparation Effort by up to 50 Percent

Customer Presentation (2)

  • Functional Safety Flow for ISO 26262 ASIL-C of D Analysis
  • Is Your Design Functionally Safe?

Video (5)

  • Functional Safety Flow for ISO 26262 ASIL-C of D Analysis
  • Is Your Design Functionally Safe?
  • The Truth about Designing for Automotive Functional Safety
  • Simplifying Fault Injection Simulations for Functional Safety Verification
  • Understanding ISO 26262 Implications for Automotive Design Teams
VIEW ALL

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