Key Benefits

We’ve worked together to optimize performance, power, and area (PPA) while speeding design and verification processes to help you design products such as IoT and mobile devices, high-performance computing servers, and embedded applications.

Achieve Best PPA


Provide highly optimized tool flows for best performance, power, and area

Faster Verification


Speed the Arm®-based design and verification process

Improve SoC Quality and Performance


Ensure IP interoperability and verification

Offerings

Over the years, our deep cooperative engineering programs join Cadence’s digital and mixed-signal design methodologies to verification flows and IP integration, and even to foundry compatibility, with Arm products including Arm Cortex®-A, Cortex-R, and Cortex-M processors; Neoverse™ processors; Mali™ GPUs, video, and display technologies; CoreLink™ System IP; Artisan® Physical IP, POP™ IP, and Fast Models.

Overview

Arm works with EDA vendors to develop EDA reference flows. Working closely with Arm, Cadence has optimized our full-flow digital solution for Arm®-based designs. Using the resulting digital implementation reference flows, you can efficiently implement your Arm core-based systems on chip (SoCs) and reach your power, performance, and area (PPA) targets much faster versus using generic EDA reference flows.

Arm utilizes Cadence® tools to develop its IP. We have early access to Arm cores, so we can tune our tool algorithms, features, and options, and can optimize our flow before the official release of the Arm cores. This lowers your risk to develop an Arm-based SoC, reduces the timeframe to meet your PPA targets, and provides expertise to help with last-mile closure.

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Overview

Developing hardware and software systems now involves integrating many IP blocks, many cores, and lots of software. To ensure that your system on chip (SoC) meets your design intent, verification technology is essential. Cadence offers verification solutions—from early software bring-up to use-case testing, debugging, and performance analysis—ideal for Arm-based SoC designs.

Collaborating with Arm, Cadence has enhanced the Arm-based system verification technologies in our System Development Suite to ensure that your Arm®-based SoCs meet design intent, minimize iterations of your interconnect, while quickly verifying and analyzing performance, and achieve faster time to market.

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Overview

The most time-consuming aspect of system-on-chip (SoC) functional verification is often the creation of a testbench that accurately stimulates and responds to the interfaces on the design under test. Since a typical SoC contains dozens of standard interfaces and multiple, layered interconnect fabrics, Verification IP (VIP) provides a huge benefit by modeling all those interfaces as components that can be plugged into a testbench and simulated along with the design under test. This offloads a substantial amount of work from the verification engineer, saving time and improving product quality.

Cadence® Verification IP for Arm® AMBA® protocols is an easy-to-use comprehensive solution that improves SoC quality and performance, providing dependable results to predict verification schedules and boost productivity.

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Overview

Get easier access to EDA tools for designs with the Arm Cortex-M0, Cortex-M3, and Cortex-A5 processors. In collaboration with Arm’s DesignStart program, Cadence offers a Hosted Design Solutions Enablement Program to accelerate your time-to-silicon with increased productivity, flexibility, and support. These products and services let you meet design requirements whether you are a start-up company or a large enterprise company seeking to exploit the volume cost benefits of an SoC.

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Overview

To reduce the time to market and simplify SoC development for IoT devices, Arm and Cadence jointly developed an IoT reference platform. The reference platform gives you commonly used functions required in an IoT design, including a processor, an IoT subsystem, and standard interfaces.

This reference platform lets designers jumpstart IoT design projects and focus aspects of the design that will differentiate their products. In addition to cost and risk factors of using third-party IP, the reference platform reduces the amount of verification needed since the various IP components have already been tested for interoperability.

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