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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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Verification

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

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IP

An open IP platform for you to customize your app-driven SoC design.

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IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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Multiphysics System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

PRODUCT CATEGORIES

  • Design Authoring
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FEATURED PRODUCTS

  • Allegro Package Designer Plus
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Computational Fluid Dynamics

AI / Machine Learning

AI IP Portfolio

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KR - Korea
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  • Taiwan - 繁體中文
  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • 기술지원 및 교육
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        • Support Process
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      • Support
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        • Custom IC / Analog / RF Design
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Custom/Analog Advanced Node

Innovative capabilities for custom/analog designs at 20nm and below 

  • Advanced-Node Solutions
  • Custom/Analog Advanced Node
  • Digital Advanced Node

Key Benefits

  • Increases quality of silicon: Re-engineered from the ground up to support the most aggressive advanced-node processes 
  • Boosts productivity: New design methodologies along with the introduction of targeted automation techniques enhance productivity by up to 5X versus traditional design tools and flows
  • Avoids costly respins: Close collaboration with leading foundries provides capabilities in the Virtuoso advanced-node platform that let you predict and manage process variability up front in the design flow
  • Industry leader in advanced-node custom design: The Virtuoso advanced-node platform supports and is certified by all major foundries for advanced technologies from 20nm down to 3nm

Innovative Capabilities for Custom/Analog Designs at 20nm and Below

System-on-chip (SoC) solutions must have the right mix of features, functionality, and performance to justify designing at advanced nodes. But the key challenges for custom/analog designers arise from the complexity of manufacturing. The Cadence® Virtuoso® advanced-node platform's innovative capabilities enable designers to take full advantage of the silicon.

Advanced Node Solution
Density gradient effect avoidance

Unique Design Challenges at 20nm, 16nm, 10nm, 7nm, 5nm, and 3nm Advanced Process Nodes

What makes designing at 20nm/16nm/14nm/10nm/7nm/5nm/3nm advanced nodes unique is the deep, complex interdependency of manufacturing and variability, on top of increasing power and performance specifications. 

Concerns include:

  • Multiple-patterning technology (MPT) and color-aware physical design, including double, triple, quadruple, and penta-patterning
  • Layout-dependent effects (LDE) and density-gradient effects (DGE), in which the layout context—what is placed near to a device—can impact device performance by as much as 30%
  • Sophisticated color-aware custom routing
  • Exponentially increasing physical design rules
  • Device variation and sensitivity
  • New transistor types (e.g., FinFETs)
Image showing Cadence Advanced Node Platform displaying graph of EM violations
EM violation avoidance

Why Design with Virtuoso Advanced-Node Platform

The Virtuoso advanced-node platform improves individual point tools to handle these challenges, as well as enables new design methodologies that allow for rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers—essential to designing efficiently at advanced-process nodes. 

The latest release of the Virtuoso advanced-node platform includes:

  • Robust support for FinFET-based designs, requiring MPT to manage device variability and sensitivity on the circuit design
  • Many enhanced interactive and automated capabilities to support a structured layout methodology with features such as core editing commands, interactive wire editor, module generators (ModGens), fully automated custom routing, and assisted placement, all design rules checking (DRC) and coloring correct
  • Unique and close integration with the Virtuoso physical verification system (PVS), enabling signoff verification support for both DRC and coloring decomposition within the Virtuoso Layout Suite
Advanced Node Solution
Multiple-patterning support and color-aware physical design
Advanced Node Solution
In-design design rule checking
  • Related Products

    • Virtuoso Layout Suite EAD
    • Virtuoso Space-Based Router
    • Liberate Characterization Solution
    • Spectre X Simulator
    • Liberate Variety Statistical Characterization
    • Virtuoso Variation Option
Resource Library

Video (20)

  • Samsung Foundry AMS Design Reference Flow - Advanced Node
  • Why a Row-Based Methodology is Required for Sub-10nm Custom Layout
  • Useful Utilities and Helpful Hacks
  • Accuracy, Performance, Capacity: Finding the Right Balance for Memory/SoC Verification
  • Improved Analog Layout Productivity Using ModGen Template-Driven Layout Reuse Methodology in Virtuoso Environment
  • CLE Layout Development Methodologies to Enhance Productivity of Full Custom I/O and Test-Chip Design
  • Advanced Layout Implementation Utilizing Analog APR Flow
  • Automated VDR Tagging and Verification Flow for Advanced Node Design
  • Improve Device Matching with Assisted Component P&R
  • Advanced Methodologies to Accelerate Your Custom Layout
  • Avoid Density Gradient Effects in 16FF+ Designs with Virtuoso Layout Suite GXL ModGens
  • Enhancing Design Productivity at STMicroelectronics with Virtuoso Custom/Analog Flow
  • Global Unichip: 20nm Testchip Tapeout with Cadence and TSMC
  • Offering Leading Edge Total Solutions - GLOBALFOUNDRIES Design Ready 14nm Eco System
  • Virtuoso IPVS for Advanced Node Design
  • Advanced Node Multi-Patterning Technologies within Virtuoso Environment
  • Custom Layout Methodologies with Virtuoso Advanced Node
  • Virtuoso Technology for Advanced Process Nodes
  • Get real-time electrical feedback on 16FF designs with Virtuoso Layout Suite for Electrically Aware Design
  • STMicroelectronics Automates Full Custom Analog Layout Flow Using Constraints

Presentation (7)

  • Samsung Foundry AMS Design Reference Flow - Advanced Node
  • Useful Utilities and Helpful Hacks
  • Improved Analog Layout Productivity Using ModGen Template-Driven Layout Reuse Methodology in Virtuoso Environment
  • CLE Layout Development Methodologies to Enhance Productivity of Full Custom I/O and Test-Chip Design
  • New Virtuoso Design Platform
  • Advanced Layout Implementation Utilizing Analog APR Flow
  • Automated VDR Tagging and Verification Flow for Advanced Node Design

Success Story Video (1)

  • Enhancing Design Productivity at STMicroelectronics with Virtuoso Custom/Analog Flow

Press Releases (17)

  • Cadence Joins Intel Foundry Services Ecosystem Alliance to Advance Chip Design Innovation
  • Cadence Wins Four 2020 TSMC OIP Partner of the Year Awards
  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process
  • Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies
  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation
  • Cadence Presented with Four 2019 TSMC Partner of the Year Awards
  • Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies
  • Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design
  • Cadence Recognized with Four 2018 TSMC Partner of the Year Awards
  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
  • Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation
  • Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout
  • Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
  • Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung’s 7LPP and 8LPP Process Technologies
  • Cadence Unveils Expanded Virtuoso Advanced-Node Platform for 7nm Processes
  • Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms
  • Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes

Webinar (4)

  • Why a Row-Based Methodology is Required for Sub-10nm Custom Layout
  • Improve Device Matching with Assisted Component P&R
  • Advanced Methodologies to Accelerate Your Custom Layout
  • Avoid Density Gradient Effects in 16FF+ Designs with Virtuoso Layout Suite GXL ModGens
VIEW ALL
Videos

Avoid Density Gradient Effects in 16FF+ Designs with Virtuoso Layout Suite GXL ModGens

Virtuoso IPVS for Advanced Node Design

Enhancing Design Productivity at STMicroelectronics with Virtuoso Custom/Analog Flow

Custom Layout Methodologies with Virtuoso Advanced Node

Virtuoso Technology for Advanced Process Nodes

Advanced Node Multi-Patterning Technologies within Virtuoso Environment

Advanced Methodologies to Accelerate Your Custom Layout

Toshiba Electronic Device Solutions Overcomes Complexities of Advanced-Node Designs

Advanced Node Layout Methodology For Memories

Why a Row-Based Methodology is Required for Sub-10nm Custom Layout

Improved Analog Layout Productivity Using ModGen Template-Driven Layout Reuse Methodology in Virtuoso Environment

News ReleasesVIEW ALL
  • Cadence Joins Intel Foundry Services Ecosystem Alliance to Advance Chip Design Innovation 02/07/2022

  • Cadence Wins Four 2020 TSMC OIP Partner of the Year Awards 11/02/2020

  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process 08/25/2020

  • Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies 06/02/2020

  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation 12/02/2019

Blogs VIEW ALL

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