Key Benefits
- Increases quality of silicon: Re-engineered from the ground up to support the most aggressive advanced-node processes
- Boosts productivity: New design methodologies along with the introduction of targeted automation techniques greatly enhance productivity of both circuit designers and layout engineers. Leveraging these flows and technologies can increase your productivity by up to 5X versus traditional design tools and flows.
- Accurately predicts and manages variability: Close collaboration with leading foundries provides capabilities within the Virtuoso® advanced-node platform that enable you to predict and manage variability up front in the design flow and avoid costly design respins due to process variability
- Industry leader in advanced-node custom design: The Virtuoso advanced-node platform supports and is certified by all major advanced 20/16/14/10/7nm technologies
Innovative capabilities for custom/analog designs at 20nm and below
It's well documented that designing at advanced-process nodes is extremely complicated and painfully expensive. With this in mind, system-on-chip (SoC) solutions must have the right mix of features, functionality, and performance to justify designing at these nodes. But of most concern to custom/analog designers are the challenges that arise from the complexity of manufacturing. The Cadence® Virtuoso advanced-node platform has an innovative set of capabilities that enables designers to take full advantage of the silicon at these process nodes.
Designing at 20nm, 16nm, 10nm, 7nm Advanced Process Nodes
What makes designing at 20nm/16nm/14nm/10nm/7nm advanced nodes unique is the deep, complex interdependency of manufacturing and variability, on top of increasing power and performance specifications.
Concerns include:
- Multiple-patterning technology (MPT) and color-aware physical design, including double, triple, quadruple, and penta-patterning
- Layout-dependent effects (LDE) and density-gradient effects (DGE), in which the layout context—what is placed near to a device—can impact device performance by as much as 30%
- Sophisticated color-aware custom routing
- Exponentially increasing physical design rules
- Device variation and sensitivity
- New transistors types (e.g., FinFETs)
Virtuoso Advanced-Node Platform
The Virtuoso advanced-node platform improves individual point tools to handle these challenges, as well as enables new design methodologies that allow for rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers—essential to designing efficiently at advanced-process nodes.
The latest release of the Virtuoso advanced-node platform includes:
- Robust support for FinFET-based designs, requiring MPT to manage device variability and sensitivity on the circuit design
- Many enhanced interactive and automated capabilities to support a structured layout methodology with features such as core editing commands, interactive wire editor, module generators (ModGens), fully automated custom routing, and assisted placement, all design rules checking (DRC) and coloring correct
- Unique and close integration with the Virtuoso physical verification system (PVS), enabling signoff verification support for both DRC and coloring decomposition within the Virtuoso Layout Suite
Press Releases (9)
- Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation
- Cadence Presented with Four 2019 TSMC Partner of the Year Awards
- Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies
- Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design
- Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
- Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation
- Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout
- Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms
- Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes
Success Story Video (1)
Video (8)
- Enhancing Design Productivity at STMicroelectronics with Virtuoso Custom/Analog Flow
- Global Unichip: 20nm Testchip Tapeout with Cadence and TSMC
- Offering Leading Edge Total Solutions - GLOBALFOUNDRIES Design Ready 14nm Eco System
- Virtuoso IPVS for Advanced Node Design
- Advanced Node Multi-Patterning Technologies within Virtuoso Environment
- Custom Layout Methodologies with Virtuoso Advanced Node
- Virtuoso Technology for Advanced Process Nodes
- STMicroelectronics Automates Full Custom Analog Layout Flow Using Constraints
