- System Design and Verification (154)
- PCB Design and Analysis (75)
- Custom IC - Analog - RF Design (75)
- Digital Design and Signoff (68)
- Simulation and Testbench Verification (40)
- Incisive Specman Elite (28)
- Acceleration and Emulation (27)
- Silicon Signoff (24)
- Palladium XP Series (23)
- Flows SDV (21)
- SI PI Analysis integrated solution (21)
- Software-driven Verification (19)
- Protium FPGA-Based Prototyping Platform (19)
- FPGA-based Prototyping (19)
- Block Implementation (19)
- Innovus Implementation System (19)
- Power-Aware Verification Methodology (17)
- Incisive Enterprise Simulator (17)
- IC Package Design and Analysis (16)
- Synthesis (15)
- Virtuoso Layout Suite (15)
- Palladium Z1 Series (14)
- SI PI Analysis Point Tools (14)
- Modus Test Solution (13)
- 테스트 (13)
- Formal and Static Verification (13)
- Hierarchical Design and Floor Planning (12)
- Library Characterization (12)
- Layout Design (12)
- Circuit Design (12)
- Perspec System Verifier (12)
- Virtual System Platform (12)
- Flows (11)
- Incisive vManager Solution (11)
- Allegro PCB Designer (11)
- Virtuoso ADE Product Suite (10)
- Liberate Trio Characterization Suite (10)
- Whiteboard Wednesdays (155)
- Tensilica Processor IP (72)
- Verification IP (71)
- Interface IP (68)
- Image Video Processing (39)
- Simulation VIP (37)
- Accelerated VIP (27)
- Denali Memory IP (27)
- USB IP (24)
- DDR IP (22)
- Memory Models (19)
- PCI Express IP (18)
- Assertion-based IP (18)
- MIPI IP (17)
- ARM AMBA (14)
- MIPI (12)
- PCI Express (11)
- HiFi Audio, Voice, Speech (11)
- ConnX Digital Signal Processing (11)
- 표시 (10)
- Ethernet IP (10)
- MIPI (10)
980 Result(s) Found
Discover how Uhnder created the world’s first digital radar chip, an impossible task without tools from Cadence. “Together we’re going to save millions of lives,” says Manju Hegde, CEO and cofounder of Uhn...
06 Dec 2019
The ENICS SoC Lab at Bar Ilan University tapedout the Israeli HiPer Consortium N16 chip (members include: Mellanox, Ceva, DSP Group, Satixfy, Ceragon, Sonics, others…) and signed-off the design using Caden...
02 Dec 2019
Tired of patchwork 3D EM analysis? Impedance discontinuity can destroy your BER and cause multiple design iterations. Using today’s 3D EM modeling tools can take you days to accurately model the interconne...
27 Nov 2019
Learn about how the new cloud-ready Clarity™ 3D Solver lets you optimize your design for true 3D system analysis. This electromagnetic (EM) solver addresses complex 3D structures on chips, packages, and PC...
27 Nov 2019
Liran Kosovizer, a TI verification manager, is a highly experienced, advanced user of UVM-e and Cadence® Specman® Elite. Liran believes in automation, structured processes, and reuse. While making the best...
20 Nov 2019
This video provides a short general overview of the main Cadence Training options and learning methods including: online (ILS) courses, live (ILT) training, Training Byte videos, and learning maps per tech...
07 Nov 2019
This demonstration of Celsius Thermal Solver shows how easy it is to perform highly-accurate electrical-thermal co-simulation. Steady-state and transient simulations are performed as well as heat transfer...
24 Oct 2019
In this week's Whiteboard Wednesdays video, Ben Gu introduces Celsius™ Thermal Solver, a new tool employing finite element analysis (FEA) techniques for thermal analysis of electronic systems. Ben explain...
23 Oct 2019
Learn how Cadence memory model Verification IP (VIP) helped Rambus with the verification of their memory subsystems allowing them to meet their time to revenue targets.
23 Oct 2019
Frank Schirrmeister from Cadence Design Systems presents in the US Pavillion at the 53rd Paris International Airshow on 20th June 2019 promoting Cadence solutions for Intelligent System Design in Aerospace...
17 Oct 2019