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Next-Generation Silicon for AI-Based ApplicationsHailo’s leading-edge solution for AI used Cadence digital design and signoff technology.
02 Mar 2021
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Cadence RTL-GDS Digital Flow Catalyzed Hailo Edge AI ProcessorDiscover how Hailo launched their Edge AI processor with performance of up to 26 TOPS using Cadence’s RTL-GDS digital flow and signoff technology.
01 Mar 2021
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Clarity 3D Solver Empowering 112G SerDes and DDR4 Design AnalysesThis video provides a detailed look at Clarity 3D Solver used in analyzing applications such as 112G SerDes and high-speed DDR4 based designs.
23 Feb 2021
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CadenceTECHTALK: Improved Debug and Package Handling for Mixed-Signal VerificationMixed-signal simulations have unique challenges whether you're running from the command line or within the Cadence® Virtuoso® platform. Join our experts in this one-hour webinar and learn ways to tackle th...
23 Feb 2021
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NA - Improved Debug and Package Handling for Mixed-Signal VerificationMixed-signal simulations have unique challenges, whether you're running from the command line or within the Cadence® Virtuoso® platform. Where are the interfaces between logic and electrical, and are they ...
23 Feb 2021
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How We Push Largest 5nm High-Performance Arm Core to 4GHz FrequencyThe race to compute performance at minimum power is for decades one of the major challenges for electronic design. It now reaches even higher level of priority when considering the increasing need for high...
10 Feb 2021
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Cadence TechTALK: How to Create Accurate ECAD Libraries from MCAD and Automate ThemAccurate libraries are key to getting quality results out of any design tool. Attend this webinar to learn how Allegro ECAD-MCAD Library Creator provides an automated way to accurately generate IPC standar...
05 Feb 2021
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Level Up Your RTL Bring-Up: Clean RTL Faster Without Simulation!Webinar – February 24 Join this webinar for an introduction to this powerful methodology—and learn best practices for getting the most out of RTL design bring-up using the JasperGold Formal Verification Pl...
05 Feb 2021
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Extending Power, Performance, and Area (PPA) Leadership using Machine LearningCadenceLIVE: India- Digital Implementation and Signoff
03 Feb 2021
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Chip Reset Methodology for Optimal Digital Design Implementation and SignoffCadenceLIVE: India- Digital Implementation and Signoff
03 Feb 2021
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