- Characterization (7)
- Liberate Trio Characterization Suite (7)
- Virtuoso Liberate MX (7)
- Custom IC - Analog - RF Design (7)
- Library Validation (7)
- Process Variation Modeling (7)
- Virtuoso Liberate AMS (7)
- Virtuoso Liberate (6)
- Virtuoso Liberate LV (6)
- Virtuoso Variety (6)
- Library Characterization (5)
- Spectre Accelerated Parallel Simulator (1)
- Spectre Circuit Simulator (1)
- Spectre eXtensive Partitioning Simulator (XPS) (1)
- Spectre RF Simulation (1)
- Virtuoso Analog Design Environment (1)
- Virtuoso Layout Suite (1)
- Virtuoso Integrated Physical Verification System (1)
- Mixed Signal Design (1)
- Virtuoso Schematic Editor (1)
- Innovus Implementation System (1)
- Genus Synthesis Solution (1)
- LDE Electrical Analyzer (1)
- Physical Verification System (1)
- Quantus QRC Extraction (1)
- Tempus Timing Signoff Solution (1)
- Voltus-Fi Custom Power Integrity Solution (1)
- Voltus IC Power Integrity Solution (1)
7 Result(s) Found
Accurate library characterization and variation modeling
Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
Cadence announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing (HPC) designs.
01 Oct 2018
Vinayak Bhat, a staff mixed-signal verification engineer at PMC-Sierra, explains how he and his team improved timing characterization of analog macros using Cadence Virtuoso Liberate AMS Mixed-Signal Chara...
23 Mar 2016
The Cadence Virtuoso Liberate AMS characterization solution is the industrys first dynamic simulation characterization solution for mixed-signal blocks. This video describes how the Liberate AMS solution ...
18 Mar 2016
Ning Jin, discusses how company overcame library characterization challenges. Ning discussed library characterization at CDNLive Silicon Valley . View her presentation, Session CUS202 in Custom/Advanced No...
31 May 2016
Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution
Watch the video to find out how the Cadence Virtuoso Liberate Characterization solution provided a robust solution to both Invecas customers and the library designers. Ankit Saxena, discusses the challenge...
08 Mar 2017
DAC 2013 Mobile Semiconductor Presentation on Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM. Discussion on Liberate MX designed for macros, Liberate MX Benchmark, Low V...
26 Aug 2015