- System Design and Verification (12)
- Power-Aware Verification Methodology (12)
- Flows SDV (11)
- Palladium XP Series (4)
- Conformal Low Power (3)
- Palladium Dynamic Power Analysis (3)
- JaperGold Verification Platform (3)
- Simulation and Testbench Verification (3)
- Incisive Enterprise Simulator (3)
- Circuit Design (2)
- Virtuoso AMS Designer (2)
- Digital Design and Signoff (2)
- Innovus Implementation System (2)
- Flows (2)
- Low Power Validation (2)
- Acceleration and Emulation (2)
- Formal and Static Verification (2)
- Custom IC - Analog - RF Design (1)
- Virtuoso ADE Assembler (1)
- Virtuoso ADE Explorer (1)
- Virtuoso ADE Product Suite (1)
- Virtuoso ADE Verifier (1)
- Virtuoso Analog Design Environment (1)
- Virtuoso Schematic Editor (1)
- Circuit Simulation (1)
- AMS Designer (1)
- Spectre Accelerated Parallel Simulator (1)
- Spectre Circuit Simulator (1)
- Spectre RF Simulation (1)
- Virtuoso Layout Suite (1)
- Layout Verification (1)
- RF Design (1)
- Block Implementation (1)
- Low Power (1)
- Quantus QRC Extraction (1)
- Tempus Timing Signoff Solution (1)
- Voltus-Fi Custom Power Integrity Solution (1)
- Voltus IC Power Integrity Solution (1)
- Palladium Z1 Series (1)
- Genus Synthesis Solution (1)
- Debug Analysis (1)
- Incisive Formal Verification Platform (1)
- Software-driven Verification (1)
To examine simulation and emulation technologies for a thorough, yet faster functional verification of low-power systems on chip (SoCs), this paper first reviews the fundamental sources and reduction techn...
By combining Palladium XP DPA with Encounter Power System TI achieved close correlation between the architects power estimation and actual silicon power consumption measurements enabling the company to del...
The design, implementation, and verification tools and flows provided by Cadence address all areas of power management and solve the SoC low-power problem.
Learn how Mohit Jain from STMicroelectronics applied Cadence Incisive Enterprise Simulator and SimVision debug capabilities for IEEE 1801 / UPF low-power verification by resusing his existing code successf...
22 Aug 2015
Shaji Kunjumohamed from Broadcom discusses Low Power Verification using CPF/IEE 1801 and Application OF Formal Verification at Chip Level. The Power Intnet Challenge is that IT touches everything. An over...
22 Mar 2016
Watch this 3-minute video to learn how Freescale verifies its next-gen low-power SoC with Cadence® power-aware x-optimism simulation. Abhinav Nawal, a member of the company's SoC verification team, walks y...
18 Mar 2016
Abhishek Jain, Technical Manager at STMicroelectronics, talks about working with the Cadence Incisive Verification Solution to deploy a UVM multi-language, low-power verification methodology resulting in e...
23 Jun 2016
In this video, Andrew Chang, MediaTek corporate vice president, talks about the challenges in creating today's smart devices complexity, push for higher performance, and the need for lower power. Learn ho...
22 Aug 2015
Antoine Dejonghe, Green Radio Program Manager at imec, highlights the use of the Cadence CPF-Driven Advanced Low-Power Solution that accelerates the company's next generation 4G wireless designs.
15 Jun 2016
Adam Sherer and Mickey Rodriguez from Cadence discuss 5 Steps to Your First Power Shut-off (PSO) Verification. Low-Power Verification Raises Silicon Quality and complex conditions open risk for bug escapes...
22 Aug 2015