Filter Results:
- System Design and Verification (23)
- Protium FPGA-Based Prototyping Platform (18)
- FPGA-based Prototyping (15)
- Protium S1 FPGA-Based Prototyping Platform (9)
- Allegro FPGA System Planner (5)
- PCB Design and Analysis (4)
- Simulation and Testbench Verification (4)
- Xcelium Parallel Simulator (4)
- Acceleration and Emulation (3)
- Palladium Z1 Series (2)
- Palladium Hybrid (2)
- Palladium XP Series (2)
- Perspec System Verifier (2)
- PCB Layout (1)
- Emulation Development Kit (1)
- Palladium Dynamic Power Analysis (1)
- QuickCycles Service (1)
- SpeedBridge Adapters (1)
- Virtual JTAG Debug Interface (1)
- SpeedBridge Adapters (1)
- Planning and Management (1)
- Incisive vManager Solution (1)
- Incisive Enterprise Simulator (1)
- Xcelium Simulation on Arm-Based Servers (1)
- Stratus High-Level Synthesis (1)
- System Development Suite (1)
|
32 Result(s) Found
|
Protium S1 FPGA-Based Prototyping PlatformThe Cadence® Protium™ S1 FPGA-Based Prototyping Platform is an advanced FPGA-based prototyping solution enabling early software development, throughput regressions, and high-performance system validation.
362 KB
|
Perspec System Verifier DatasheetPerspec System Verifier is a software-driven system-on-chip (SoC) verification solution. The Perspec System Verifier improves SoC quality and saves time by reducing development effort for complex SoC-level...
1 MB
|
Protium FPGA-Based Prototyping Platform DatasheetProtium FPGA-Based Prototyping Platform is an advanced FPGA-based prototyping solution enabling early software development, throughput regressions, and high-performance system validation
141 KB
|
vManager Metric-Driven Signoff Platform DatasheetA powerful, scalable, and automated verification planning and management solution supporting multi-user, multi-engine, multi-analysis, and multi-projects simultaneously
953 KB
|
Stratus High-Level Synthesis DatasheetStratus High-Level Synthesis HLS automatically creates high-quality register-transfer level RTL design implementations for ASIC, system-on-chip SoC, and FPGA targets from high-level C++/SystemC description...
547 KB
|
Allegro FPGA System Planner DatasheetCadence Allegro FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin-count FPGAs on the PCB board.
2 MB
|
ASIC Prototyping Simplified Technical PaperAllegro FPGA System Planner has been found to double or triple the productivity and cut the overall schedule in half. In this application note, we will walk you through a complete FPGA board for ASIC proto...
890 KB
|
Palladium Z1 Enterprise Emulation Platform DatasheetPalladium Z1 unifies best-in-class simulation acceleration and emulation technologies into a platform that is 8X more densely integrated and is optimized for multi-user emulation throughput and efficiency.
1 MB
|
Xcelium Parallel Logic Simulation DatasheetThe Cadence Xcelium Parallel Simulator is the third generation of digital simulation. At its core is the first production-proven multi-core engine. Unified with that engine are the industry’s fastest singl...
614 KB
|
Protium S1 Single-FPGA Board DatasheetPart of the Cadence Protium S1 FPGA-Based Prototyping Platform, the Protium S1 Single-FPGA Board is an affordable and high-performance solution for IP validation and early software development. It is fully...
709 KB
|
|
Display:
|