Filter Results:
- Custom IC - Analog - RF Design (9)
- Quantus QRC Extraction (9)
- Innovus Implementation System (9)
- Tempus Timing Signoff Solution (8)
- Virtuoso ADE Product Suite (8)
- Voltus-Fi Custom Power Integrity Solution (7)
- Virtuoso Layout Suite (7)
- Voltus IC Power Integrity Solution (7)
- Virtuoso Schematic Editor (6)
- Genus Synthesis Solution (6)
- Virtuoso Liberate (5)
- Liberate Trio Characterization Suite (5)
- Pegasus Verification System (4)
- Virtuoso Liberate AMS (4)
- Spectre Accelerated Parallel Simulator (4)
- Spectre eXtensive Partitioning Simulator (XPS) (4)
- Virtuoso Layout Suite for Electrically Aware Design (4)
- Virtuoso Liberate MX (4)
- Virtuoso Variety (4)
- Virtuoso ADE Verifier (4)
- Virtuoso ADE Explorer (4)
- Virtuoso ADE Assembler (4)
- Virtuoso Liberate LV (3)
- Characterization (3)
- Library Validation (3)
- Process Variation Modeling (3)
- Spectre Circuit Simulator (3)
- Spectre RF Option (3)
- Spectre X Simulator (3)
- Virtuoso Variation Option (3)
- Virtuoso RF Solution (3)
- Library Characterization (2)
- Synthesis (2)
- Virtuoso Schematic Editor (2)
- Digital Design and Signoff (2)
- Virtuoso Analog Design Environment (2)
- LDE Electrical Analyzer (2)
- Physical Verification System (2)
- Virtuoso Layout Suite EAD (2)
- Virtuoso Analog Design Environment (2)
- Spectre Simulation Platform (2)
- Space-Based Router (2)
- Spectre RF Simulation (1)
- Virtuoso Schematic Editor (1)
- Flows (1)
- Flows - Circuit Design (1)
- Legato Reliability Solution (1)
- Circuit Simulation (1)
- Electromagnetic Analysis (1)
- Layout Co-Design (1)
- Layout Design (1)
- Virtuoso Layout Suite EAD (1)
- What's New in Virtuoso (1)
- Layout Verification (1)
- Physical Verification System (1)
- Virtuoso Integrated Physical Verification System (1)
- Mixed Signal Design (1)
- Virtuoso Analog Design Environment (1)
- Virtuoso Schematic Editor (1)
- Spectre Accelerated Parallel Simulator (1)
- Virtuoso Visualization and Analysis (1)
- Spectre Accelerated Parallel Simulator (1)
- Spectre Circuit Simulator (1)
- Spectre eXtensive Partitioning Simulator (XPS) (1)
- Virtuoso Schematic Editor (1)
- Celebrate 25 Years Of Virtuoso (1)
- Block Implementation (1)
- Spectre Circuit Simulator (1)
- Flows (1)
- Advanced Node (1)
- Innovus Implementation Solution (1)
- PVS Overview (1)
Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System InnovationNational Instruments Corporation and Cadence Design Systems, Inc. announced a system innovation strategic alliance to create an integrated design to test flow, leveraging reusable data and test IP from ele...
02 Dec 2019
|
Cadence Digital and Custom Flows Achieve Certification for TSMC N3 ProcessCadence announced that its digital full flow and custom tool suite has been optimized for TSMC’s 3nm (N3) process technology.
25 Aug 2020
|
Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process TechnologiesCadence announced that its digital full flow and custom/analog tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies.
02 Jun 2020
|
Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production DesignCadence announced that it has collaborated with TSMC to enable customers’ production delivery of next-generation SoC designs for mobile, HPC, 5G and AI applications on TSMC’s 5nm FinFET process technology.
22 Apr 2019
|
Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process TechnologiesCadence announced that its digital and signoff full flow and custom/analog tools have achieved certification on TSMC’s N6 and N5/N5P process technologies.
25 Sep 2019
|
Cadence Presented with Four 2019 TSMC Partner of the Year AwardsCadence today announced that it has been presented with four TSMC Partner of the Year awards at the TSMC 2019 Open Innovation Platform® (OIP) Ecosystem Forum.
30 Oct 2019
|
Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven LayoutCadence introduced major enhancements to its Cadence® Virtuoso® custom IC design platform that improve electronic system and IC design productivity.
10 Apr 2018
|
Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design InnovationCadence announced its continued collaboration with TSMC to further 5nm and 7nm+ FinFET design innovation for mobile and high-performance computing (HPC) platforms.
01 May 2018
|
Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design CreationCadence announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing (HPC) designs.
01 Oct 2018
|
Cadence Recognized with Four 2018 TSMC Partner of the Year AwardsCadence announced that it has received four TSMC Partner of the Year awards at this year’s TSMC Open Innovation Platform® (OIP) Ecosystem Forum.
09 Oct 2018
|
|
Display:
|