Lowering Leakage Power in ARM Cortex-A17 Processor-based SoCs at GLOBALFOUNDRIES

Ralf Flemming, a design engineer at GLOBALFOUNDRIES, explains how the company used a Cadence low-power digital design and signoff flow to lower leakage power to 1.5% with 2GHz maximum frequency in its ARM Cortex-A17 processor-based family of SoC reference designs.

마지막 수정 날짜: March 18, 2016