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    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
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          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
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      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
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  • Cadence Digital Full Flow Achieves Certification for GlobalFoundries® 12LP/12LP+ Process Platforms

Cadence Digital Full Flow Achieves Certification for GlobalFoundries® 12LP/12LP+ Process Platforms

19 May 2022

Highlights:

  • Certification enables customers to advance the design of aerospace, hyperscale computing, AI, mobile and consumer applications using Cadence and GF® technologies
  • Cadence digital full flow optimized for the GF 12LP/LP+ process platforms enables mutual customers to reach PPA goals faster and deliver new products to market with shorter design cycles

SAN JOSE, Calif.— Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Cadence® digital full flow achieved certification for the GlobalFoundries (GF) 12LP/12LP+ process platforms to advance the design of aerospace, hyperscale computing, AI, mobile and consumer applications. The certification confirms that the Cadence digital full flow has met all of GF’s accuracy, integration and quality of results (QoR) criteria specified for the 12LP/12LP+ process platforms, enabling mutual customers to reach power, performance, and area (PPA) goals faster and to deliver new products to market with shorter design cycles.

The Cadence tools were optimized for the GF 12LP/12LP+ process platforms and certified using an industry-standard high-efficiency processor core. The certified tools include the Innovus™ Implementation System, Genus™ Synthesis Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Quantus™ Extraction Solution, Litho Physical Analyzer (LPA) and Pegasus™ Verification System. For more information on the Cadence digital full flow tools for advanced-node design, please visit www.cadence.com/go/dffcertgf12lp.

The digital full flow provides additional benefits to GF 12LP/12LP+ users through the Cadence iSpatial technology, which allows a seamless transition from Genus physical synthesis to Innovus implementation using a common user interface and database. The flow also provides unified implementation, timing- and IR-signoff engines, offering enhanced signoff convergence by concurrently closing the design for all physical, timing and reliability targets.

“The Cadence digital full flow certification on our 12LP/12LP+ process platforms validates the accuracy of the implementation and signoff methodology,” said Richard Trihy, vice president of design enablement at GF. “Through our collaboration, we’re providing our customers with a trusted solution to speed up the implementation process, which is particularly critical for those creating emerging aerospace, hyperscale computing and AI applications and experiencing great pressure to deliver new products to market quickly.”

“Through the integration and innovation offered by our digital full flow, customers using GF’s 12LP/12LP+ process platforms can confidently converge on their PPA targets faster,” said Kam Kittrell, senior group director, product management, in the Digital & Signoff Group at Cadence. “The thorough correlation checks performed by GF on the Cadence digital full flow gives users an added level of assurance that they can implement high-performance designs quickly in order to remain competitive in their respective markets.”

The Cadence digital full flow provides better predictability and a faster path to design closure and supports Cadence’s Intelligent System Design™ strategy, which enables SoC design excellence.

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

© 2022 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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