Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies

Highlights:

• Cadence digital, signoff, and custom/analog tools achieve latest DRM and SPICE certification for TSMC N6 and N5 process technologies
• Cadence integrated digital full flow features enhanced physical optimization and timing signoff closure that’s certified for TSMC’s strategic HPC and mobile platforms

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its digital full flow and custom/analog tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies. The Cadence^® tool suites have achieved Design Rule Manual (DRM) and SPICE certification for TSMC’s latest N6 and N5 process technologies. These advancements allow next-generation mobile application development at N6 and N5 and hyperscale application development on N5 with updated reference flows and methodologies. Cadence and TSMC are working with customers on production designs on TSMC’s advanced processes including N7, N6 and N5 and have enabled real-world tapeouts across those nodes worldwide.

The certified tool suites support the Cadence Intelligent System Design^™ strategy, enabling customers to achieve SoC design excellence. Cadence’s integrated flow ensures it is fully convergent and all tools work together seamlessly. Customers can download the corresponding N6 and N5 process design kits (PDKs) to begin design projects now. To learn more about the Cadence advanced-node solutions, visit www.cadence.com/go/advancednodepr.  

N6 and N5 Digital and Signoff Tool Suite Certification

Cadence has further improved its fully integrated digital full flow, which continues to be certified on both TSMC’s N6 and N5 process technologies. The certified Cadence digital full flow features enhanced physical optimization and timing signoff closure. It includes the Innovus^™ Implementation System, Liberate^™ Characterization, Liberate Variety^™ Statistical Characterization, Quantus^™ Extraction Solution, Tempus^™ Timing Signoff Solution, Voltus^™ IC Power Integrity Solution and Pegasus^™ Verification System. Additionally, the Genus^™ Synthesis Solution and its latest predictive iSpatial technology is enabled for these process technologies for both mobile and hyperscale designs.

The Cadence digital and signoff tool suite and available reference flows help customers achieve better power, performance and area (PPA) while designing on TSMC’s N6 and N5 process technologies. Some of the updated tool suite improvements include enhanced EUV layer support, a new chip integration checker for floorplan design rules, and additions to via pillar, autoNDR and advanced MIMCAP support.

N6 and N5 Custom/Analog Tool Suite Certification

The Cadence custom/analog tool suite has been certified on TSMC’s N6 and N5 process technologies. The certification includes the Virtuoso^® Custom IC design platform, consisting of the Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso ADE Product Suite, the Voltus-Fi Custom Power Integrity Solution, and the Spectre^® Circuit Simulation Platform, including the new Spectre X Simulator.

Cadence continues to improve custom design methodologies and capabilities within the Virtuoso Advanced-Node Platform tailored for TSMC’s advanced process technologies. Customers continue to achieve better custom design throughput versus traditional non-structured design methodologies by leveraging advanced capabilities within the Virtuoso platform. Custom/analog enhancements for TSMC’s advanced process technologies incorporate an accelerated custom placement and routing methodology, which enables customers to improve productivity and meet power, multiple patterning, density and electro migration requirements. Interactive and automatic placement with advanced color engine support features have been enabled in N6. Additionally, the platform provides expanded design rule constraint support with area-based rules, universal polygrid snapping, asymmetric coloring rule, mimcap layer support, voltage-dependent rule (VDR) checking, Width-based Spacing Patterns (WSPs), electrically-aware design (EAD) to enable correct-by-construction EM handling, and analog cell support.

“Through our longstanding collaboration with Cadence, we’re continuing to enable customers in the most competitive markets to take advantage of our latest advanced process technologies,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “The joint efforts combining Cadence’s leading edge design tools with the most advanced TSMC process technologies are helping our customers achieve silicon success for mobile, AI/ML and hyperscale systems applications, and we’re looking forward to seeing all the new innovations make a positive impact on the industry.”

“We’ve worked to ensure that our digital and custom/analog solutions met TSMC’s criteria for production use on the latest N5 and N6 process technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Due to our close collaboration with TSMC, our customers are already working on production designs and demonstrating successful results.”

About Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and health. For six years in a row, Fortune Magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

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