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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
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        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
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        • Automotive
        • AI / Machine Learning
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        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
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        • Arm-Based Solutions
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  • 2019
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  • 2 Jul 2019

Cadence Digital Full Flow Achieves Certification for Samsung Foundry 5LPE Process Technology

SAN JOSE, Calif., 02 Jul 2019

Highlights:

  • Samsung Foundry confirmed that the Cadence tools meet its stringent technology requirements, providing customers with optimal PPA
  • Cadence flow was certified using the Arm Cortex-A53 and Cortex-A57 cores for the 5LPE process

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the Cadence® digital full flow has achieved certification for the Samsung Foundry 5nm Low-Power Early (5LPE) process with Extreme Ultraviolet (EUV) lithography technology. The Cadence tools have been confirmed to meet Samsung Foundry’s technology requirements, which let customers who produce high-end products for the mobile, networking, server and automotive markets attain optimal power, performance and area (PPA).

“As part of our longstanding collaboration with Cadence, we’ve confirmed that its digital full-flow meets and exceeds the requirements for designing with the 5LPE process technology,” said Jung Yun Choi, vice president of the Design Technology Team at Samsung Electronics. “By deploying the latest Cadence market-leading digital flow and Samsung advanced-node technology, customers can confidently create innovative designs for emerging high-end markets such as the mobile, networking, server, automotive, industrial, and artificial intelligence markets.”

The Cadence digital flow was certified by Samsung using the Arm Cortex®-A53 and Cortex-A57 cores for the 5LPE process. To ensure the Cadence flow is easy to understand and use, it incorporates a Cadence flow manager with a common user interface across the complete toolset. The Cadence tools optimized for the Samsung 5LPE process include the Genus™ Synthesis Solution, Innovus™ Implementation System, Joules™ RTL Power Solution, Conformal® Equivalence Checking, Conformal Low Power, Modus™ DFT Software Solution, Quantus™ Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Physical Verification System, Litho Physical Analyzer and Cadence CMP Predictor. For more information on the Cadence digital and signoff full flow, please visit www.cadence.com/go/dands5lpe.   

“Through our ongoing collaboration with Samsung Foundry, we’re making it faster and easier for customers to create advanced-node designs in an age of increasing complexity,” said KT Moore, vice president, product management in the Digital & Signoff Group at Cadence. “The powerful combination of the Cadence digital implementation and signoff full-flow, Samsung 5LPE process, and Arm cores gives customers access to the latest technologies to optimize PPA and create tomorrow’s innovations.”

The integrated Cadence digital full-flow provides a fast path to design closure and better predictability and supports the company’s overall Intelligent System Design™ strategy, enabling advanced-node system-on-chip (SoC) design excellence.

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.

For more information, please contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. Arm and Cortex are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All other trademarks are the property of their respective owners.

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For more information, please contact:

Cadence Newsroom

408.944.7039

newsroom@cadence.com

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