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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
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      • AI / Machine Learning
      • AI IP Portfolio
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  • 23 Apr 2019

Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology

Full suite of Cadence digital and signoff, custom/analog, and IC package and PCB analysis tools optimized for TSMC SoIC chip stacking technology

SAN JOSE, Calif., 23 Apr 2019

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced TSMC certified Cadence’s design solutions for the new TSMC System-on-Integrated-Chips (TSMC-SoIC™) 3D advanced chip stacking technology, which integrates heterogenous chips—including logic ICs and memory—that are fabricated on different process nodes onto a single chip stack for a subsequent packaging process. A full suite of Cadence® digital and signoff, custom/analog, and IC package and PCB analysis tools have been optimized for TSMC’s SoIC chip stacking technology, enabling mutual customers that require heterogenous chipset integration capabilities to create complex designs more efficiently.

For more information on the Cadence solutions that support the TSMC-SoIC advanced packaging technology, visit www.cadence.com/go/soic.    

SoIC, TSMC’s innovative multi-chip stacking techniques, expands upon TSMC’s 3D Wafer-on-Wafer (WoW) and Chip-on-Wafer (CoW) technologies and address the diverse design requirements for emerging applications, including 5G, AI, IoT and automotive applications. TSMC and Cadence collaborated to enhance tools, methodologies and flows, supporting mutual customers to manage the overall connectivity and verification of their chip integration solutions as part of the overall design. The entire design cycle is enabled with multiple 3D featured tools working together.

The Cadence tools in the flow include the Innovus™ Implementation System, Quantus™ Extraction Solution, Voltus™ IC Power Integrity Solution, Tempus™ Timing Signoff Solution, Physical Verification System (PVS), Virtuoso® custom IC design platform, SiP Layout, OrbitIO™ interconnect designer, Sigrity™ PowerSI® 3D EM Extraction Option, Sigrity PowerDC™ technology, Sigrity XcitePI™ Extraction, Sigrity XtractIM™ technology and Sigrity SystemSI™ technology.

“Cadence and TSMC have a rich history of collaboration, which continues as we today deliver innovative capabilities to support the new advanced TSMC-SoIC chip stacking technology,” said Tom Beckley, senior vice president and general manager, Custom IC & PCB Group at Cadence. “The SoIC solution empowers our mutual customers to employ the latest 3D techniques using our optimized tools, flows and methodologies to meet tight design delivery deadlines.”

“The Cadence tools, reference flows and methodologies for our new SoIC advanced chip stacking technology complement our well-established InFO, WoW and CoWoS® chip integration solutions, providing customers with even more flexibility to integrate multiple die onto a single device using 3D stacking techniques,” said Suk Lee, TSMC senior director, Design Infrastructure Management Division. “Our ongoing collaboration with Cadence on advanced packaging technologies has resulted in helping our mutual customers to achieve efficient and successful product designs targeting 5G, AI, IoT and automotive applications.”

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.

For more information, please contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

© 2019 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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