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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-XFi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
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  • 6 Sep 2017

Cadence Announces Legato Memory Solution, Industry’s First Integrated Memory Design and Verification Solution

Delivers up to 2X runtime improvement compared to existing point tool solutions

SAN JOSE, Calif., 06 Sep 2017

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Cadence® Legato™ Memory Solution, the industry’s first integrated solution for memory design and verification. The Legato Memory Solution eliminates the complexity of piecing together point tools for multiple design and verification tasks and can lead to productivity gains of up to 2X when compared with previous point tool offerings. To learn more about the Cadence Legato Memory Solution, please visit www.cadence.com/go/memorysolution.

The first-of-its-kind Legato Memory Solution’s cohesive design environment automates design steps and lets customers use the innovative Cadence toolset to deliver products to market faster. The solution includes new patent-pending Cadence Super Sweep technology that utilizes existing simulation databases for multi-corner and Monte Carlo analysis, allowing customers to improve both runtime and simulation throughput.

The technology capabilities included with the Cadence Legato Memory Solution improve overall design productivity and are as follows:

  • Bitcell design and verification environment: Customers can design the bitcell, including variation analysis, without ever having to leave the design environment.
  • Memory compiler design and verification environment: Customers can design and verify full memory arrays within the Legato Memory Solution and access the new Super Sweep technology to maximize accuracy and simulation throughput for advanced-node designs.
  • Memory characterization environment: Customers can create Liberty format models of the memory for system-on-chip (SoC) full-chip analysis. The tight integration between memory characterization and circuit simulation provides additional accuracy and performance improvements that can’t be achieved by point tools.

“As a world-leading supplier of System-on-Chip solutions, focused on imaging, networking and computing technologies that drive a wide variety of applications, it is critical that we accurately simulate memory instances to minimize area and power consumption of System-on-Chip,” said Yoshifumi Okamoto, corporate executive vice president & CTO at Socionext. “Through our use of the Cadence Legato Memory Solution, we have experienced a 2X productivity gain when compared with our point solution and successfully taped out 12nm memory macro designs for our System-on-Chip solutions, and we can confirm good correlation between simulation result and silicon measurement.”

“Long simulation times and a high rate of inaccuracy have become bottlenecks in the SoC design cycle schedule,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “The new Legato Memory Solution combines patented technologies interleaved with our existing, proven Virtuoso® Liberate™ MX Memory Characterization Solution, Spectre® eXtensive Partitioning Simulator (XPS) and Virtuoso Variation Analysis solutions to improve designer productivity and enable our customers to meet stringent design schedules.”

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.

For more information, please contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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For more information, please contact:

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newsroom@cadence.com

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