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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
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        • Planning and Management
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        • Verification IP
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        • Flows
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        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
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    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
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        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
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        • What's New in Allegro
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  • 06 June 2016

Cadence Expands Collaboration with ARM to Accelerate Custom SoC and IoT System Designs with Industry’s First End-to-End Hosted Design Solution

SAN JOSE, Calif., 06 Jun 2016

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the industry’s first complete hosted end-to-end solution to enable designers to accelerate their custom SoC and Internet of Things (IoT) design process using ARM Cortex®-M processors. This offering accelerates mixed-signal SoC design for IoT, incorporating the ARM IoT Subsystem for Cortex-M processors and Cadence’s interface IP and unified mixed-signal implementation solution, now optimized specifically for Cortex-M cores. 

To further lower barriers to innovation, Cadence has also joined the ARM DesignStart™ program to provide tools and IP for designs incorporating the Cortex-M0 processor. 

The ARM IoT Subsystem and DesignStart packages provide the most comprehensive solution a designer may need – including tools and IP – to accelerate time-to-silicon for their IoT applications. The combined mixed-signal IoT flow for both the IoT subsystem package and DesignStart are available on the Cadence Hosted Design Solution (HDS), a software-as-a-service (SaaS) model which offers quick access to EDA tools, support and methodologies. With this secure solution, users can log in anywhere, anytime and gain access to tools without needing installation or the supporting hardware for it. 

Optimizing IoT system design requires a deep understanding of tool flows, methodology, IP, packaging and software. ARM has developed a test chip to showcase this complete IoT implementation using a complete Cadence tool flow, the ARM IoT Subsystem and Cadence IP. The test chip includes processor IP, ARM Artisan® physical IP, wireless connectivity solutions, interface IP, software, design tools (both front- and back-end), optimized design methodology and scripts. 

“ARM is seeing a growing demand for custom SoCs as our partners continue to focus on improving costs, power and functionality,” said Vincent Korstanje, vice president of marketing, systems & software group, ARM. “The collaboration with Cadence makes designing IoT platforms and custom SoCs even easier, further accelerating time to market.” 

“As the leader in system design enablement, we are collaborating with ARM to provide a complete solution of optimized IP, tool flows and subsystems to enable customers to deliver emerging Internet of Things applications,” said Dr. Chi-Ping Hsu, senior vice president and chief strategy officer, Cadence. “Through our continued collaboration with ARM on both ARM DesignStart and the ARM IoT Subsystem for Cortex-M, we’ve optimized our EDA tools and methodology to complement ARM IP to bring designers from concept to silicon much faster.” 

Cadence’s mixed-signal solution is production proven and has addressed the needs of the mixed signal design community for over 20 years, delivering thousands of successful tapeouts. The seamless integration of the Virtuoso® custom design platform with the Innovus™ Implementation System, and the Spectre® custom verification platform with the Incisive® Enterprise Simulator provides the basis for ARM-based IoT design and verification. For more information, visit: www.cadence.com/solutions/ms. 


About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

For more information, please contact:

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© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Incisive, Spectre, Virtuoso and the Cadence logo are registered trademarks and Innovus is a trademark of Cadence Design Systems, Inc. in the United States and other countries. ARM, Artisan and Cortex are registered trademarks and DesignStart is a trademark of ARM Ltd. (or its subsidiaries) in the EU and/or elsewhere. All other trademarks are the property of their respective owners.

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