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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-XFi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
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  • 03 Sep 2014

TSMC Adopts Cadence Solutions for 16nm FinFET Library Characterization

Virtuoso Liberate Characterization Solution and Spectre Circuit Simulator together double the speed of characterization for 16nm FinFET libraries

SAN JOSE, Calif., 02 Sep 2014

Highlights:
  • Output libraries meet TSMC's stringent accuracy targets for 16nm FinFET STA correlation
  • 16nm FinFET v1.0 libraries characterized by Cadence solution are now deployed for production and STA tool certification
  • 16nm FinFET library characterization tool setting available at TSMC-Online
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that TSMC has adopted Cadence® solutions for 16nm FinFET library characterization. Developed in collaboration between Cadence and TSMC, the library characterization tool setting is available to TSMC customers for download on TSMC-Online. The setting is based on Cadence Virtuoso® Liberate® Characterization Solution and Spectre® Circuit Simulator, and includes environment setup and sample templates for TSMC standard cells.

Utilizing native Spectre API integration, the combination of the Liberate solution and Spectre Circuit Simulator delivers superior convergence and accuracy, enabling mutual customers to speed up their library characterization cycle. In testing performed with TSMC, the combined Cadence characterization and simulation solution reduced the turnaround time by half for 16nm FinFET standard and complex cell-characterization cycles. As a result, TSMC has incorporated the Liberate solution with Spectre Circuit Simulator into its library characterization production flow for the latest 16nm FinFET libraries. Libraries characterized by the Cadence characterization solution were used in the 16nm FinFET v1.0 static timing analysis (STA) tool certification, including the Cadence Tempus™ Timing Signoff Solution and other STA tools. The reference kit gives TSMC customers the tools needed to enable re-characterization that addresses their specific design challenges with a consistent methodology that meets TSMC's stringent accuracy and performance requirements. The Liberate solution also continues to support third-party circuit simulators.

"Library characterization is an important part of 16nm FinFET collaboration with TSMC," said Tom Beckley, senior vice president, Custom IC & PCB Group at Cadence. "Through this collaboration, customers can benefit from improved throughput, accuracy and capacity required for 16nm FinFET library characterization."

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and services is available here.

For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com


© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Spectre and Virtuoso are registered trademarks of, and Liberate and Tempus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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