Cadence Redefines Verification Planning and Management with Incisive vManager Solution

HIGHLIGHTS:

• All-new verification planning and management solution delivers multi-user, multi-engine, multi-project and multi-analysis capabilities
• MDV methodology improves verification productivity by 2X or more
• Integrated commercial SQL database technology enables broad scalability
• Seamless interoperability with Incisive verification platform and Palladium XP Verification Computing Platform

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today introduced an all-new Incisive® vManager™ solution, a verification planning and management solution enabled by client/server technology to address the growing verification closure challenge driven by increasing design size and complexity. The Incisive vManager solution, with its metric-driven verification (MDV) methodology, improves verification productivity by 2X or greater over traditional methods by combining executable verification plans, coverage optimization techniques, collaborative management utilities, deep failure and coverage analysis, and clear visibility to see when to shift resources.

Part of the Cadence® Incisive functional verification platform, the Incisive vManager solution utilizes commercial SQL database technology and enables broad scalability from small intellectual property (IP) projects to gigascale system-on-chip (SoC) designs. Additionally, to ensure SoC developers have a consistent methodology for design quality enhancements, the Incisive vManager solution supports several MDV extensions addressing applications including acceleration, low power and mixed-signal verification.

Incisive vManager Key Features

• Multi-user support: Allows unlimited simultaneous users for improved collaboration and better visibility into team-based verification
• Multi-engine support: Operates seamlessly with Incisive Enterprise Simulator, Incisive Formal Verifier and Palladium® XP Verification Computing Platform
• Multi-project capability: Enables multiple projects to be managed independently within the same environment-an industry first. Users can view project status, progress over time, and key metrics enabling verification signoff
• Multi-analysis feature: With the fully integrated Incisive Metrics Center, users can analyze coverage, test failures, perform failure triage, create and analyze executable plans, find coverage holes and design problems, all to determine focus areas to complete verification

"The move to gigascale SoC designs with larger and more dispersed design teams and increased time-to-market pressures has created new verification management challenges for companies," said Andy Eliopoulos, vice president, research and development, Advanced Verification Solutions at Cadence. "With the Incisive vManager solution, Cadence is solving these challenges and launching a new era of verification management. For the first time, design teams will have the ability to support multiple users, better coordinate and control the verification process, and dramatically improve their productivity."

For more detailed information on the Incisive vManager solution, visit www.cadence.com/news/vmanager.

Incisive vManager Customers Speak Out
"The Incisive vManager solution has been very well accepted by our design and verification teams because it's really straightforward, intuitive and easy to use. The Incisive vManager solution helps us with project visibility, which improves our verification productivity," said Mirella Negro Marcigaglia, verification manager, STMicroelectronics.

"Driven by ever-more-demanding use cases, the growing complexity of our DSPs require a highly powerful verification tool capable of addressing billions of coverage points. The new Incisive vManager solution allows us to merge and analyze our latest cores' databases on a scale never before possible, improving our productivity and providing faster time-to-market. As we begin to take advantage of the multi-user capability, we are confident we will gain even further improvements," said Ran Snir, VLSI director at CEVA.