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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
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      • AI IP Portfolio
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  • 11 Dec 2014

Cadence Perspec System Verifier Delivers Up to 10X Productivity Improvement in System-on-Chip Verification

SAN JOSE, Calif., 10 Dec 2014

HIGHLIGHTS:
  • Reduces complex use-case scenario development effort for SoC verification from weeks to days
  • Automates traditionally manual, and often complex, system-level coverage-driven test development
  • Improves SoC quality by accelerating the development of complex software-driven tests and integrated debug to reproduce, find and fix complex SoC-level bugs
Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced the Cadence® Perspec ™ System Verifier platform for use-case scenario-based software-driven system-on-chip (SoC) verification. Using an intuitive graphical specification of system-level verification scenarios and a definition of the SoC topology and actions, this new verification solution automates system-level coverage-driven test development using constraint-solving technology, delivering up to 10X productivity improvement in SoC verification versus typical manual test development. A part of the Cadence System Development Suite, Perspec System Verifier reduces complex test development from weeks to days, while also allowing design teams to reproduce, find and fix complex bugs to improve overall SoC quality.

Perspec System Verifier is currently available. For more information, visit www.cadence.com/news/perspec.

Perspec System Verifier delivers increased productivity and SoC quality through several key features, including:
  • A Unified Modeling Language (UML) based view of system-level actions and resources that, combined with powerful solver technology, creates an intuitive view of complex and hard-to-test system-level use-case interactions
  • Solver technology, which automates the generation of portable tests to deliver complete coverage of system-level scenarios based on chip constraints and the scope of the scenarios to verify SoC-level features for functionality, performance and power
  • Tests that run on all pre-silicon verification platforms including simulation, acceleration and emulation, and virtual and FPGA prototyping, which can be further used to validate actual silicon
"Today's verification teams face a challenge in that the bottom-up approach to IP verification does not extend to the SoC level, and they are looking for an opportunity to move to top-down scenario-based verification in order to extend traditional approaches like UVM and achieve better coverage," said Charlie Huang, executive vice president, Worldwide Field Operations and System & Verification Group at Cadence. "With its SoC-level constraint-solving technology, Perspec System Verifier is enabling our customers to create tests previously not feasible, increasing their confidence that they are meeting SoC functional requirements while speeding time to market."

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com


© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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