Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that Tilera Corp. achieved an 8X run-time performance improvement for power signoff of its largest design to date, the TILE-Gx72 processor using the new Cadence® Voltus™ IC Power Integrity Solution. Without any loss of accuracy, Tilera cut power signoff runtime for this highly integrated 72 core system-on-a-chip design from 65 hours to 8 hours for dynamic analysis and from 12 hours to 2.5 hours for static analysis.
"As the global leader in manycore processors, it is critical that Tilera selects the best design signoff technologies to achieve optimum performance-per-watt in our products while meeting aggressive time-to-market requirements," said John F. Brown III, vice president of IC Engineering at Tilera. "The Voltus product's advanced parallel computation significantly reduced the power signoff runtime on our most recent TILE-Gx processor. This superior performance allows our engineers to cut the power signoff iteration procedure from days to hours and achieve the best in quality in our designs."
The enabling technologies behind the Voltus IC Power Integrity Solution include a new massively distributed parallel power integrity engine and hierarchical analysis technology that can run designs of up to 1 billion instances and with up to 10X performance gains over competing products. The Voltus solution can be used as a standalone power signoff tool, but it provides even greater value to its users through its integration with several key Cadence tools - the Tempus™, Encounter®, Palladium®, Allegro®, Sigrity®, and Virtuoso® platforms. This combined design implementation and signoff eco-system provides the industry's most efficient and fastest design closure flow.
Learn more about Voltus IC Power Integrity Solution at
www.cadence.com/news/Voltus.
