- Academic 1 : Domain-Specific AI: Practices and Applications
Xin Li, Duke University - Academic 2 : VLSI Mask Optimization: From Shallow To Deep Learning
Bei Yu, Chinese University of Hong Kong - Academic 3 : Formal Verification of Two Cases: RISC-V RV32I and Hardware Trojan-embedded DNN
Yean-Ru Chen, National Cheng Kung University - Academic 4 : Collaboration Between Academia and Industry Using Tensilica DSP IP
Anton Klotz, Cadence
Conference Proceedings
AI Research and Academic Network
Custom Analog and Mixed Signal
- Analog 1 : Collaboration with Cadence for UMC 28HPC+ AMS Reference Flow
Yueh Guey Chou, UMC - Analog 5 : Safe Operation Area Check &Floating Node Check
Po Sheng Chen, Nuvoton - Analog 6 : Leverage AMS in Mixed-Signal Power Management IC Design for Powerful and Effective Flow
Jesse Wang, ON Semiconductor - Analog 7 : Early Detection of Circuit Reliability Issues with Schematic-Level Reliability Verification
I-Lun Tseng, Zhao Chuan Lee, Vikas Tripathi, Chun Ming Tommy Yip, and Jonathan Ong, GLOBALFOUNDRIES - Analog 8 : MathWorks and Cadence Integration: Design and Verification of Mixed-Signal Systems
Phoebe Li, TeraSoft
Digital Full Flow Design
- DIF 2 : Using Machine Learning to Improve PPA
Feng-Yuan Lu, MediaTek - DIF 3 : Beyond the Noise: What's the Efficient Methodology to Fix Glitch in N7?
YIWEI CHEN, MediaTek - DIF 4 : IR Closure Flow From Specification to Sign-off
Ichiro Lin, Faraday - DIF 5 : The Challenge and Experience Sharing on 7nm Multi-Billion Gate Design Implementation
DS Fu, GUC - DIF 6 : Best Practices for Arm Cortex-A55 Energy Efficient Implementation Flows in POPTM IP on 22nm
Herbert Shen, Arm - DIF 7 : Early Detection of Cu Pooling Hotspots Using Advanced CMP Modeling
Single Hsu, UMC
Ethan Wang, Cadence
IC Design on the Cloud
- Cloud 2 : EDA on AWS - Accelerating Design Innovation
Jhen-Wei Huang, AWS - Cloud 3 : Microsoft Azure for Silicon Design
Andy Chan, Microsoft - Cloud 4 : The Cadence Cloud Portfolio
Craig Johnson, Cadence
PCB Design and System Analysis
- PCB 1 : True 3D Analysis of Large Geometrics with Clarity 3D Solver
Jian Liu, Cadence - PCB 3 : Study on DDR Tabbed-Routing Structure
John Lin, Lenovo - PCB 4 : 30 Years of Digital Transformation
Yi-Chien Huang, Footprintku - PCB 5 : An Efficient PDN / IR Drop / SI Check Verification with Sigrity
Ming Chen, Chunghwa Precision Test - PCB 7 : Correlation of E-T Co-Sim with IR Camera Measurement on Multi-Board System Design
Hank Lin, ASUS
System Design and Verification
- Verification 1 : Optimizing Verification Throughput for a Connected World
Michael Young, Cadence - Verification 2 : Streamline the Verification Flow and Apply to DisplayPort 8K4K Design
Philip (Ming-Fu) Tsai, GUC - Verification 5 : Using JasperGold to Verify Full Function of Design From Input to Output
Pham Van Khich, Renesas - Verification 6 : JasperGold FPV for Post-Silicon Debug
Hugh Lo, Realtek
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