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      Digital Design and Signoff Overview

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    • Custom IC
      Custom IC / Analog/ RF Design Overview

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    • Verification
      System Design and Verification Overview

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    • System Analysis
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  • India 2016
  • Conference Highlights
  • Proceedings

Conference Proceedings

Alternate Papers
  • Session Alt_1 : PCIe 4.0: Designing and Testing Against an Evolving Specification
    Devanshu Bajaj – Cadence Design Systems
  • Session Alt_2 : UVM Vault
    Srinivasan Venkataramanan - CVC
    PraneshSairam A - CVC
    Santhosh Kumar M - CVC
Custom Analog - Implementation
  • Session CI1 : 28FDSOI Memory Implementation with SPD – A Smart Placer
    Vikas Chelani - STMicroelectronics
    Arvinder Singh Rooprai - STMicroelectronics
    Ishita Dhawan - Cadence Design Systems
  • Session CI2 : Cycle Time Improvement of Mixed Signal SoC Designs Through OA Interoperable Flow
    Penchal Kumar Gajula - Texas Instruments
    Gaurav Varshney - Texas Instruments
    Ankur chavan - Cadence Design Systems
    Devesh Jain - Cadence Design Systems
    Brajesh Heda - Cadence Design System
  • Session CI3 : Electromigration Analysis Of Data Converter Circuits With VoltusFi
    Shubham Gupta - STMicroelectronics
    Vivek Bhatia - STMicroelectronics
    Chandrajit Debnath - STMicroelectronics
    Abhay Apte - Cadence Design Systems
  • Session CI4 : Layout Design Time Reduction by Interactive DRC Checking at Advanced Node FinFet Process Using Virtuoso iPVS2
    Anuj Solanki - Freescale Semiconductors, NXP Group of Companies
    Ankit Jain - Freescale Semiconductors, NXP Group of Companies
    Vishesh Kumar - Cadence Design Systems
  • Session CI5 : Enhancing Design Productivity Using Virtuoso EAD
    Avinash B S - Applied Micro
  • Session CI6 : Analyzing Layout Dependent Effects (LDE) on Deep Submicron Technologies Using Cadence Virtuoso Platform
    Preet Yadav - Freescale Semiconductors, NXP Group of Companies
    Abhay Apte - Cadence Design Systems
  • Session CI7 : Automatic Parasitic Model Generator (APMG) For CMOS Image Sensor
    Mukesh Rao Engla Syam - ON Semiconductor
    V. Penchala Reddy Gaddam - ON Semiconductor
  • Session CI8 : A Novel EMIR Methodology For Embedded Memories
    Pankaj Agarwal - NXP Semiconductors
    Achint Prakash - NXP Semiconductors
    Deepti Saini - NXP Semiconductors
    Jwalant Mishra - NXP Semiconductors
    Patrick Van De Steeg - NXP Semiconductors
  • Session CI9 : Quick Way Of Implementing Analog Layout And Enhanced Reusability & Productivity Using Grid Pattern Editor (GPE) And Topology Based Routing In ModGen
    Varun Kumar Dwivedi - STMicroelectronics
    Nishant Sharma - STMicroelectronics
    Ankita Chaudhary - STMicroelectronics
    Vishesh Kumar - Cadence Design System
Custom Analog - Verification
  • Session CS1 : Accelerating in depth yield improvement analysis on advanced technology nodes using new Virtuoso ADE (Explorer/Assembler/Variation option) flow
    Preet Yadav - Freescale Semiconductors, NXP Group of Companies
    Abhay Apte - Cadence Design Systems
    Ashish Patni - Cadence Design Systems
  • Session CS2 : Reliability: Accounting for Device Aging and Self-Heating in Advanced Nodes
    Hany Elhak – Cadence Design System
  • Session CS3 : Electromigration Characterization Across Frequency Range for Standard Cells using Liberate and Its Usage At Design Level
    Ankit Saxena - Invecas Technology
    Atul Kumar Kashyap - Invecas Technology
    Kartikay Sharma - Cadence Design Systems
  • Session CS4 : Comprehensive Automated Design Validation Suite for Standard Cells
    Nidhi Bhatia - Texas Instruments
    Keshav Chintamani - Texas Instruments
    Reena Elangovan - Texas Instruments
  • Session CS5 : A Case Study of Automation Flow for Mixed Signal SoC Verification
    Sujit Bhat - Sankalp Semiconductor
    Pradeepkumar Marikundam - Sankalp Semiconductor
  • Session CS6 : Analog Mixed-Signal Behavioral Modeling Using Cadence SMG
    Vani Priya - STMicroelectronics
    Alessandro Valerio - STMicroelectronics
    Abhay Apte - Cadence Design Systems
    Chao Xing - Cadence Design Systems
  • Session CS7 : Real Valued Modeling for CMOS Image Sensors
    Prashanth Jnanendra - On Semiconductor
    Prasad Viswanath - On Semiconductor
  • Session CS8 : Forget Connect Modules For Once - A Universal, Transparent Connect Module Methodology For DMS And AMS Co-Simulation
    Lakshmanan Balasubramanian - Texas Instruments
    Nadeem Hussain Tehsildar - Texas Instruments
    Bharath Kumar Poluri - Texas Instruments
    Vijay Kumar Sankaran - Cadence Design Systems
  • Session CS9 : Mixed Signal Verification With Verilog-AMS and SV Test Bench
    Amol Dhok - NXP Semiconductors
    Srinivas R - NXP Semiconductors
PCB and IC Packaging Design
  • Session PCB1 : Application of Integrated PSPICE and MATLAB Environment for the Development of Two-Wheeler Automotive Product
    Saif Zaidi - Tata Elxsi
    Sunitha TVN - Tata Elxsi
    Parag P Kshirsagar - Tata Elxsi
    Rajesh Nikam - Tata Elxsi
  • Session PCB2 : Influence of Vias and Stubs on Signal Integrity and Minimizing Their Impact
    Anoop Sasidharan - Qwave
    Manoj S - Qwave
  • Session PCB3 : Intelligent Data Transfer Between Design, Fab and Assembly Using IPC-2581
    D. Vijayakumar – Tessolve
    Kameshvaran Muthusamy – Tessolve
  • Session PCB4 : High Speed Signal Routing Techniques & Challenges
    Sabarish Pulliyasseri - Seagate Technology HDD India
    Goutham Sabavat - Seagate Technology HDD India
    Subramanian Ramanathan - Seagate Technology HDD India
  • Session PCB5 : Importance of Orientation of Power Plane
    Ashish Bhandari - Caliber Interconnect Solutions
    Gowrisankar Arumugasamy - Caliber Interconnect Solutions
    Sabari Siva Sankaran N - Caliber Interconnect Solutions
    Shanmugapriya Devadasan - Caliber Interconnect Solutions
  • Session PCB6 : “Global Library Part Management” Using Cadence CIS and ODBC With ERP/SQL Backend and Time Zone Replication
    Binu Gibson – Sanmina-SCI Technology India
    Ponraj Muthunadar - Sanmina-SCI Technology India
  • Session PCB7 : PCB “Sign off” for Manufacturing
    Amba Prasad - Tejas Networks
    Dhiraj Kiran - Tejas Networks
  • Session PCB9 : Power Plane Noise Coupling to High Speed Signals in PCBs
    Goutham Sabavat - Seagate Technology HDD India
System to Signoff - Digital Front-End Design
  • Session FED1 : Abstract Boundary Model Based Test Architecture
    Sreekanth G Pai - GLOBALFOUNDRIES
    Kavitha Shankar - GLOBALFOUNDRIES
    Hardik Bhagat - GLOBALFOUNDRIES
    Kelly Ockunzzi - GLOBALFOUNDRIES
    Richard Grupp - GLOBALFOUNDRIES
  • Session FED3 : Enabling Conformal ECO Methodology for Quicker Derivative Designs Closure
    Archana Reddy Bommineni - Xilinx
    Sidharth Panda - Cadence Design Systems
  • Session FED4 : Scalable Hierarchical Synthesis Methodology for SoCs
    Ajay G - Asarva Chips and Technologies
    Ramesh T. Parthasarathi - Asarva Chips and Technologies
  • Session FED6 : Improving Random Resistance Coverage At RTL
    Raghu Gaurav G - IBM
    Sumit Kumar Panigrahi - IBM
    Venkatesh Lingaiah - Cadence Design Systems
  • Session FED7 : Optimized LEC Flow
    Remya Mohan Nair - Microsemi
    Swaroop A - Cadence Design Sytems
    Samir Attar - Cadence Design System
  • Session FED8 : Zero Pin Retention Methodology For Area Benefits In Genus Synthesis And Complete Power Aware Verification Using Conformal Low Power
    Amit Kumar - Qualcomm
    Sidharth Panda - Cadence Design Systems
    Mayank Jindal - Cadence Design Systems
    Shankar Raj V - Cadence Design Systems
System to Signoff - Digital Implementation
  • Session DIG1 : Physical Implementation Tricks & Techniques With Innovus for Large Designs
    Pranav Murthy - Broadcom
    George Abraham - Cadence Design Systems
  • Session DIG2 : Hybrid Clock Trees with Multi-Tap CCOpt
    Vikas Joshi - GLOBALFOUNDRIES
    Greg Ford - GLOBALFOUNDRIES
    Shashank Sreekanta - GLOBALFOUNDRIES
  • Session DIG3 : Implementing ARM Cortex-A73 & Cortex-A35 With Arm POP IP And Cadence Innovus – "PPA Improvement And Improving Turn Around Time"
    Amresh Sahoo - ARM
    Jaspreet Singh - ARM
    Shourya Shukla - ARM
    Payal Agarwal - ARM
  • Session DIG4 : Maximizing PPA (Pushing The Performance Boundaries) Of A Complex Core Design Using Global Foundries 22FDX Technology With The Latest Cadence Implementation & Signoff Tools/Flow
    Ramprasad Gopannagari - Invecas Technology
    Nagaraj Kommaraboina - Cadence Design Systems
  • Session DIG5 : Ultra-Low Power Implementation of A53 ARM Core “Every MW Counts”
    Sumit Vyas - Freescale Semiconductors, NXP Group of Companies
    Puneet Dodeja - Freescale Semiconductors, NXP Group of Companies
  • Session DIG6 : Thin Channel Based SOC Implementation Using Innovus
    Varinder Kumar - MediaTek
    Bhimender Saini - Mediatek
    Arun Kumar - Cadence Design Systems
    Karthik Kandasamy - Cadence Design Systems
    Tapaswi Khamar - Cadence Design Systems
  • Session DIG7 : Tiling: An Advanced Approach for Logic Partitioning of Netlists
    Arnab Halder - Qualcomm
    Himakiran - Qualcomm
    Nikhil Murgai - Cadence Design Systems
  • Session DIG8 : TSMC 10FF Implementation Challenges And Methodologies For High Performance CPU Design
    Mohamed Saud Jaffer - ARM
    Vasant S - ARM
  • Session DIG9 : Implementation Challenges Faced During Physical Implementation Of 5M+ (Top Level) Design Targeting Gigahertz Frequencies Using Innovus
    Davinder Aggarwal - STMicroelectronics
    Anil Yadav - STMicroelectronics
    Suresh Kumar Aggarwal - STMicroelectronics
    Prashant Kumar Vishen - Cadence Design System
System to Signoff - Signoff
  • Session SO1 : 2.5D Static Timing Analysis Using PTM
    Rambabu S - Open-Silicon
    Somshekar - Open-Silicon
  • Session SO2 : Analyzing Digital Self Heating Effect and Its Impact On EM Using Voltus
    Paul Mathew - NXP Semiconductors
    Sidharth Kumar - Cadence Design Systems
    N Kannan - NXP Semiconductors
  • Session SO3 : Ensuring Quality IR-Drop Signoff Analysis With Voltus
    Subhadeep Ghosh - Texas Instruments
    Shruti Kasetty - Texas Instruments
    Ajoy Mandal - Texas Instruments
    Suravi Bhowmik - Texas Instruments
    Manu Balusamy R - Cadence Design Systems
    Sidharth Kumar Panda - Cadence Design Systems
  • Session SO5 : Handling Reliability Issues : Early And Accurately
    Karuna Doomra - eInfochips
  • Session SO6 : Post-Mask ECOs Timing Closure With Metal Fill Using Cadence PVS in EDI/Innovus
    Ankit Jain - Freescale Semiconductors, NXP Group of Companies
    Tilak Wadhwa - Freescale Semiconductors, NXP Group of Companies
  • Session SO7 : To Enable Spice Based PGV Generation And IR Drop Analysis Flow For GF22FDX Technology Using Voltus
    Ramprasad Gopannagari - Invecas Technology
    Ankit Saxena - Invecas Technology
  • Session SO8 : PBA Driven Convergent Implementation and Signoff in Hierarchical Designs
    Syed Shakir Iqbal - LG Soft India
  • Session SO9 : Signoff Timing Analysis Challenges and Solutions for Hierarchical Designs
    Madhur Kashyap - Freescale Semiconductors, NXP Group of Companies
    Amit Agarwal - Freescale Semiconductors, NXP Group of Companies
    Manish Jain - Freescale Semiconductors, NXP Group of Companies
    Priya Khandelwal - Freescale Semiconductors, NXP Grou
System Verification - Advanced Methodology
  • Session AVM1 : A Novel Approach For Automating Verification And Performance Analysis of High Speed Cache Coherent Interconnect Subsystems In SoC
    Shailesh Wardhen - Broadcom
    Mukundan KN - Broadcom
    Gnaneshwara Tatuskar - Cadence Design Systems
    Yoga Priya - Cadence Design Systems
  • Session AVM2 : Code Coverage On System Verilog Testbench As A Verification Signoff Metric
    Ponnambalam Lakshmanan - Analog Devices
    Kunal Jani - Analog Devices
    Swati Ramachandran - Cadence Design Systems
  • Session AVM3 : Co-Simulation With RTL Verification IP to Verify SystemC Models
    Simranjit Singh - Infineon Technologies
    Prasanth Sasidharan - Infineon Technologies
  • Session AVM4 : Fault Verification Of Safety Centric Automotive Mixed Signal Chip
    Justin Jacob - NXP Semiconductors
    Harish Bodappatti - NXP Semiconductors
    Manikandan Panchapakesan - NXP Semiconductors
    Lokesh Babu P - Cadence Design Systems
  • Session AVM5 : Highly Controllable and Efficient Verification IP Architecture for Layered Protocol
    Ankit Agarwal - Samsung Semiconductor India R&D
    Garima Srivastava - Samsung Semiconductor India R&D
  • Session AVM6 : Methodology for Faster and Exhaustive Verification of A Mixed Signal Subsystem
    Sandeep Kumar Bojja - Analog Devices
    Kunal Jani - Analog Devices
    Jai Siddi - Analog Devices
    Lokesh Babu P - Cadence Design System
  • Session AVM7 : Techniques To Automate UVM Testbench And Stimulus To Achieve At Least 30% Of Verification
    Mohana Krishna P - Xilinx
  • Session AVM8 : Usage of Advanced Verification Concepts in SystemVerilog Verification Environment
    Sougata Bhattacharjee - Mindtree
    Chandana Nallangi - Mindtree
    Mahesh Pai - Mindtree
System Verification - Formal
  • Session FOR1 : Formal - Quicker Quality Improver
    Sandeep Bojja - Analog Devices
    Kunal Jani - Analog Devices
    Nitin Neralkar - Cadence Design Systems
  • Session FOR2 : Functional Safety Analysis Demystified With Cadence Safety Verification Solution
    Abhishek Kumar - Texas Instruments
    Prasanth V. - Texas Instruments
    Lokesh Babu P - Cadence Design Systems
  • Session FOR3 : Paradigm Shift in RTL Design Quality Using Jasper Apps
    Rahul Harihara Iyer - Samsung Semiconductor India R&D
    Garima Srivastava - Samsung Semiconductor India R&D
    Purushotam - Samsung Semiconductor India R&D
    Pradeep B - Cadence Design Systems
  • Session FOR4 : Performance Improved Formal Verification Using Cadence JasperGold Apps
    Suwin Sam Oommen - Wipro
    Pallavi Kuruvinashetty - Cadence Design Systems
  • Session FOR5 : Usage of Jasper for DFT (Design for Test) Controlability Checks
    Reju Radhakrishnan - Broadcom
    Aman Tyagi - Broadcom
    Rahul Garg - Broadcom
  • Session FOR6 : Usage of FV On Verifying A Serial Protocol – Case Study
    Vinod Kumar Paparaju - Texas Instruments
  • Session FOR7 : “Formal” Driven Post-SI Validation
    Praveen Revankar - Infineon Technologies
    Bhavana Kandiga - Infineon Technologies
    Vijay Chachra - Infineon Technologies
    Nitin Neralkar - Cadence Design Systems
  • Session FOR8 : JasperGold LPV App Approach For Power Verification of Complex Chip. Is It Really Good Return On Investment?
    Vasantha Kumar B P - Qualcomm
    Sumit P - Qualcomm
    Raghavendra Javagal - Qualcomm
System Verification - Hardware-Assisted
  • Session HW1 : An Efficient Methodology for LBIST Safe Stating and xbounding Signoff using Emulation
    Abhinav Gaur - NXP Semiconductors
    Gaurav Jain - NXP Semiconductors
    Yogesh Mittal - NXP Semiconductors
  • Session HW2 : Emulation Platform For A MIPI M-PHY Based Flash Device Controller Using Palladium XP Emulator And An M-PHY Speedbridge Solution
    Subrahmanya Sastry Mangipudi - Sandisk - A Western Digital Brand
    Rama Mohana Reddy Yenamala - Sandisk - A Western Digital Brand
    Sreeekanth Varma Dantuluri - Sandisk - A Western Digital Brand
    Prasad Pattadakal - Sandisk - A Western Digital Brand
  • Session HW3 : Accelerating SoC Verification Using Emulation Platform
    Jeevan Kharadkar - Open-Silicon
    Mitesh Thakkar - Open Silicon
  • Session HW4 : Addressing Pre-Silicon Validation Challenges With Protium
    Hari Kumar K - Broadcom
    Sakthikumaran Samiappa - Broadcom
    Anil Kumar TS - Cadence Design Systems
  • Session HW5 : Enhancing Transaction Based Acceleration Performance Using Efficient SCE-MI Modelling
    Ponnambalam Lakshmanan - Analog Devices
    Anilkumar TS - Cadence Design Systems
  • Session HW6 : Migration of In-Circuit Environment With Dynamic Target to IXCOM for Accelerated Code Coverage and Software Quality
    Jahangir Shaikh - Broadcom
    Praveen Tiwari - Cadence Design Systems
  • Session HW7 : Transaction Based Bus Analyzer for Multi-Core Performance Analysis
    Pragati Singhal - Broadcom
    Sarin Chandran - Broadcom
    Merolin Gold - Broadcom
  • Session HW8 : Next Generation Cadence Emulation Platform – Palladium Z1 Overview
    Praveen Tiwari - Cadence Design Systems
System Verification - Invited Paper
  • Session SV_Invited_Paper : Conquering System Level Issues With LPDDR3 IP Flexibility
    Mitesh Thakkar - Open-Silicon
    Devendra Godbole - Open-Silicon
System Verification - Productivity
  • Session PRO1 : Efficient And Scalable Low Power Verification (CPF) Flow
    Harish M. - Texas Instruments
    Mangesh Dhantole - Texas Instruments
    Ashish Dwivedi - Texas Instruments
  • Session PRO2 : Verification Methodology of Hardware Enabled Algorithmic Tester (HEAT) Engine For Memory Subsystems
    Prajakta Rohom - Open-Silicon
  • Session PRO3 : Centralized and Automated Framework for SoC Verification Management and Tracking
    Gaurav Jain - NXP Semiconductors
    Anshul Singhal - Cadence Design Systems
  • Session PRO4 : Comprehensive and Efficient GLS using Innovative Apps
    Rupinjeet Marwah - Texas Instruments
    Prashantkumar Sonavane - Texas Instruments
    Arif Mohammed - Texas Instruments
    Vinay Rawat - Cadence Design Systems
  • Session PRO5 : Unified Multilanguage (Open Architecture) Hierarchy Solution For SoC (Top Level) Verification
    Vikram Dabre - Microsemi
    Basavaraj Koujalagi - Microsemi
    Rajratna Chauhan - Microsemi
  • Session PRO6 : Verification Management & Regression Productivity Improvement using vManager
    Anantharaj Thalaimalai Vanaraj - Sandisk - A Western Digital Brand
    Ashok Pulluru - Sandisk - A Western Digital Brand
    Arushi Bhat - Sandisk - A Western Digital Brand
    Sundararajan Ananthakrishnan – Cadence Design Systems
    Swati Ramachandran - Cad
  • Session PRO7 : Verification of Low Power Design Techniques Using CPF
    Dorababu Balam - Lattice Semiconductor
    Uday Kumar Garimella - Lattice Semiconductor
  • Session PRO8 : Accelerate Verification Productivity using Indago Debug Analyzer
    Ponnambalam Lakshmanan - Analog Devices
    Swati Ramachandran - Cadence Design Systems

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