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    • デジタル設計／サインオフ
      デジタル設計／サインオフ 概要

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      カスタムIC／アナログ／RF設計概要

      Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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  • Verilog Language and Application

Verilog Language and Application

Instructor-Led Schedule
日付 バージョン 国 場所
Scheduled upon demandOn demand お問い合せINQUIRE

Course Description

受講日数： 3日間コース

価格： お一人様 135,000 円 (消費税別、お二人様以上にてお申込み下さい)

※開催日程、開催場所に関しましてのご相談、お問合せはjapan_esg@cadence.comまで お問合せ下さい

概要： Verilog HDL を使用した回路の構造記述、動作記述の方法と、NC-Verilog の実行方法を学習します。

Learning Objectives

コースカリキュラム：

    1日目：

    • Verilog HDLの基本文法と構成
    • SimVision GUI

    ２日目：

    • 機能記述レベルのモデリング

    ３日目：

    • 機能記述レベルの応用（タスク、ファンクション）
    • ゲートレベル・シミュレーション
    • ライブラリ・サーチ
    • バック・アノテーション

    Software Used in This Course

    • Incisive Enterprise Simulator XL and Genus
  • Incisive 15.1

    • Audience

    受講対象者：

    • UNIX / LINUX の基礎知識をお持ちの方
    • 論理回路設計、または論理設計CADに従事されている方
    Course ID: 82110

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