Fastest Simulator to Achieve Verification Closure for IP and SoC Designs

Cadence Xcelium Logic Simulator provides best-in-class core engine performance for SystemVerilog, VHDL, SystemC®e, UVM, mixed-signal, low power, and X-propagation. It leverages a set of domain-specific apps, including mixed-signal, machine learning-based test compression, and functional safety, that enable design teams to achieve verification closure early for IP and SoC designs.

Industry-Leading Simulation

Broad Language Support

Support for SystemVerilog, VHDL, SystemC, e, UVM, and IEEE UPF standards

Best-in-Class Performance

Automated parallel and incremental build technologies to support the compilation of big SoC designs and best-in-class simulation engines for best regression throughput, including a multi-core engine to speed-up long-running test cases

Accelerate with Apps

Xcelium Apps such as mixed-signal, machine learning-based test compression, and functional safety for ease of mixing and matching different technologies needed throughout the design and verification cycles

Portfolio of Apps

Xcelium Apps work natively with the Xcelium Logic Simulator and enable design teams to achieve the highest verification performance at both the IP and full-chip level of modern SoC designs.

Machine Learning

The Xcelium Machine Learning (ML) App utilizes proprietary ML technology to reduce regression times by learning from previous regression runs and guiding the Xcelium randomization kernel to either achieve the same coverage with significantly less simulation cycles or catch more bugs around specific coverage points of interest.


The Xcelium Mixed-Signal App enables native co-simulation with Cadence Spectre SPICE analog simulation, as well as advanced SystemVerilog real number model-based simulation.


The Xcelium Multi-Core (MC) App significantly reduces runtime for long-running high activity tests by multi-threading the Xcelium kernel, such as on gate-level design for test pattern simulations.


The Xcelium Safety App enables serial and concurrent fault simulation, which when combined with Cadence’s safety verification full flow, comprising Jasper Safety, vManager Safety, and Midas Safety Planner, enables the highest performance safety campaign execution for ISO 26262 compliance.


The Xcelium PowerPlayback (PPB) App enables massively parallel Xcelium replay of waveforms captured by Palladium emulation onto a timing-annotated gate-level netlist for glitch-accurate power estimation of multi-billion gate SoC designs.

X-Pessimism Removal

The Xcelium X-Pessimism Removal (XPR) App shortens debug time by using advanced algorithms to make the propagation of “X” values in simulation more accurate.

See what customers have to say about Xcelium Logic Simulator

Xcelium simulation is part of the broader Cadence verification full flow and supports the company’s Intelligent System Design strategy, enabling SoC design excellence.