overview
Fastest Simulator to Achieve Verification Closure for IP and SoC Designs
Cadence Xcelium Logic Simulator provides best-in-class core engine performance for SystemVerilog, VHDL, SystemC®, e, UVM, mixed-signal, low power, and X-propagation. It leverages a set of domain-specific apps, including mixed-signal, machine learning-based test compression, and functional safety, that enable design teams to achieve verification closure early for IP and SoC designs.
Key Benefits
Industry-Leading Simulation
Broad Language Support
Support for SystemVerilog, VHDL, SystemC, e, UVM, and IEEE UPF standards
Best-in-Class Performance
Automated parallel and incremental build technologies to support the compilation of big SoC designs and best-in-class simulation engines for best regression throughput, including a multi-core engine to speed-up long-running test cases
Accelerate with Apps
Xcelium Apps such as mixed-signal, machine learning-based test compression, and functional safety for ease of mixing and matching different technologies needed throughout the design and verification cycles
Portfolio of Apps
Xcelium Apps work natively with the Xcelium Logic Simulator and enable design teams to achieve the highest verification performance at both the IP and full-chip level of modern SoC designs.
The Xcelium SimAI App harnesses the power of machine learning technology. It builds models from regressions run in the Xcelium simulator, enabling the generation of new regressions with specific targets. This includes efficient soak testing of the entire design or specific areas and improved regression efficiency. The app also features cousin bug hunting, a unique capability that uses information from difficult-to-hit failures to expose cousin bugs. With these advanced machine learning techniques, SimAI offers the potential for a significant boost in productivity, promising an exciting future for our users.
The Xcelium Mixed-Signal App enables native co-simulation with Cadence Spectre SPICE analog simulation, as well as advanced SystemVerilog real number model-based simulation.
The Xcelium Multi-Core (MC) App significantly reduces runtime for long-running high activity tests by multi-threading the Xcelium kernel, such as on gate-level design for test pattern simulations.
The Xcelium Safety App is ISO 26262 certified and enables serial and concurrent fault simulation, which when combined with Cadence’s safety verification full flow, comprising Jasper Safety, vManager Safety, and Midas Safety Planner, enables the highest performance safety campaign execution for ISO 26262 compliance.
The Xcelium PowerPlayback (PPB) App enables massively parallel Xcelium replay of waveforms captured by Palladium emulation onto a timing-annotated gate-level netlist for glitch-accurate power estimation of multi-billion gate SoC designs.
The Xcelium X-Pessimism Removal (XPR) App shortens debug time by using advanced algorithms to make the propagation of “X” values in simulation more accurate.
Podcast Series
Espresso and Electronics – Quick Sips of EDA Wisdom
resources
CUSTOMER STORIES
See what customers have to say about Xcelium Logic Simulator
We use the Xcelium Logic Simulator for our advanced AI/ML and IoT designs, helping accelerate our simulation tasks. We also utilize the Xcelium DMS App to verify our mixed-signal designs. With the Xcelium simulator, we can achieve verification closure and meet our time-to-market goals.
Edward Youssoufian, Vice President of Engineering, Alif Semiconductor
We have extensive experience using the Xcelium Simulator, and the new Xcelium Apps are a useful extension. Our automotive chips must adhere to the ISO 26262 standard, and the Xcelium Safety App has helped us ensure compliance and identify complex bugs using state-of-the-art verification techniques.
Yi Gu, SoC Design Director, AutoChips
The introduction of Xcelium Apps, including the Xcelium PowerPlayback App, allows us to accurately calculate power consumption and tailor the Xcelium Logic Simulator to match our verification demands, ensuring we have the correct functionality and can meet our aggressive time-to-market goals.
Yee-Wei Huang, Vice President and Spokesman, Realtek
By incorporating the Xcelium Machine Learning App as part of our verification flow, we were able to accelerate coverage convergence with fewer regression tests. This helps us meet our aggressive deadlines while maximizing verification performance and overall verification efficiency.
Tatsuya Kamei, Distinguished Engineer, Automotive SoC Business Division, Renesas Electronics
Our team has used Xcelium Logic Simulation to address our verification needs, and the Xcelium Multi-Core App allows us to shorten long-running DFT pattern simulations using multiple cores. Xcelium Apps enable timely validation closure, and we plan to use them in our verification flow.
Roberto Mattiuzzo, Design Manager, Microcontrollers & Digital ICs Group, RF & Communication Division, STMicroelectronics
related products
Xcelium simulation is part of the broader Cadence verification full flow and supports the company’s Intelligent System Design strategy, enabling SoC design excellence.
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