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- Takes a formal-first approach to control and status register (CSR) configuration, so properties and subsequent verification are truly exhaustive vs simulation-based approaches
- Allows the capture of register specifications in familiar textual formats
- Expedites debug, using absolute minimum-length waveforms to show erroneous behaviors
Enhanced with a customized GUI for results analysis, the Cadence® Jasper™ Control and Status Register (CSR) App allows the specifications of control and status register configurations and behavioral descriptions in open, familiar formats—comma-separated values (CSV) or IP-XACT XML files. You won’t need to know or learn SystemVerilog Assertions (SVA). In a matter of hours, the Jasper CSR App automatically generates register checks from the definition table and proceeds to exhaustively verify that the register-transfer level (RTL) implementation of the registers behaves as specified. Using this app, you’ll be able to find deep bugs weeks and months sooner than you can with simulation-based flows.
A modern system on chip (SoC) has many CSRs—even small IP blocks can have hundreds of such registers. Writing testbenches to verify even the most basic read/write behaviors is a time-consuming chore that doesn’t scale easily. While some engineers may think it is straightforward to verify read operations and write operations to a CSR, the verification complexity increases exponentially when advanced features are used, such as register aliasing, bit masks and byte enable, concurrent hardware and software accesses, access latencies, register remapping according to operation modes, protected versus unprotected transactions, locking conditions, modified write semantic, and read actions.
The Jasper CSR App automatically generates properties and captures register interaction, latency, and read/write semantics. The tool optimizes properties for formal first, providing faster wall clock runtime and better proof performance. When used in concert with our Jasper Visualize™ Interactive Debug Environment and QuietTrace™ debugging capability, debug is significantly easier and faster.
- Ability to load register specifications in open, human, and machine-readable CSV or IP-XACT XML files
- Enables productivity and throughput by allowing multiple proofs to be kicked off in parallel with the Jasper ProofGrid™ Intelligent Resource Manager, while proof jobs can be managed and tracked using ProofGrid Manager in a regression mode
Press Releases (4)
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
- Cadence Announces Next-Generation JasperGold Formal Verification Platform
- Cadence Completes Acquisition of Jasper Design Automation
- Cadence Redefines Verification Planning and Management with Incisive vManager Solution
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