業界最先端のCadence Verification Suite
この10年、検証がより複雑化し、開発者にとって大きな課題となってきています。一方、検証のソリューションの改善は逐次的に過ぎなかったため、「検証ギャップ」がより大きくなってしまいました。
Cadence® Verification Suite は、このギャップを埋めるために、業界最先端の、JasperGold®フォーマル検証プラットフォームとPalladium® Z1 エンタープライズ・エミュレーション・システムに、2つの新機軸の高速ソリューション、Xcelium™ 並列シミュレータおよびProtium™ S1 FPGAベース・プロトタイピング・プラットフォームを組み合わせたソリューションです。
最短の所要時間と高品質の予測可能性
あらゆるマーケットセグメントで電子製品が高度化してきており、その基盤であるハードウェアとソフトウェア開発、その両者の統合は、複雑化の一途をたどっています。早期のソフトウェア開発、ハードウェアの検証、ハードウェアとソフトウェアの統合、統合したシステムの検証は、開発コスト、プロジェクト・スケジュール、リスクが増大しており、大きな課題となっています。
Cadence Verification Suiteを使用すれば、システム統合時間を最大50%短縮でき、知財（IP）開発、システム・オン・チップ（SoC）統合、ハードウェアとソフトウェアのコンカレント開発を加速できます。図1に示すとおり、この検証セットはコアエンジン、検証ファブリックテクノロジー、これらテクノロジーで展開するソリューションにより構成されています。
Core engines, each developed to provide best-in-class technology, include:
- Formal: JasperGold Formal Verification Platform
- Simulation: Xcelium Parallel Logic Simulator, Specman® Elite
- Emulation: Palladium Z1 Enterprise Emulation Platform
- FPGA Prototyping: Protium S1 Desktop Prototyping Platform
The verification fabric provides automation, debug, tracking, management, and measurement of verification tasks across verification flows and engines, which improves productivity and increases team collaboration and productivity.
Verification fabric technologies include:
- Protocol verification: Verification IP
- Metric-driven verification: vManager™ Metric-Driven Signoff Platform
- Design and verification debug: Indago™ Debug Platform
- Portable use-case stimulus: Perspec™ System Verifier
Solutions in the Verification Suite are predefined flows and best practices to address common challenges, including total throughput for the shortest project schedule, metric-driven signoff for quality, and application-specific challenges for mobile, networking and servers, automotive, consumer and internet of things (IoT), aerospace and defense, and other vertical segments.
Our Verification Suite engines, fabric technologies, and solutions support a broad range of industry standards, are open for third-party integration, and are further augmented by our ecosystem partners, including Arm and many others.
Resource Library VIEW ALL
Video (168)
- TI Verification Expert Shares Their PSS UVM Synergy Experience
- Prototyping for Embedded Software Development—It’s Not Mission Impossible
- Prototyping Billion-Gate Designs with Protium X1 Prototyping System
- Arm and Cadence collaborate on Arm Neoverse N1 platform to advance Cloud-to-Edge infrastructure
- Designing a “First-Time-Right” Wi-Fi HaLow Baseband in less than 6 Months
- Dynamic Software Analysis in Virtual Platforms- Ericsson Expert Insights
- Xilinx - Cadence Virtual System Platform to Accelerate Product Development
- Protium X1 Enables Multi-Billion Gate FPGA-Prototypes to Run at Multi-MHz Speed
- Performance and Debug – Get Both, Using Specman
- Early Firmware Development on Palladium and Protium, Enables 1st Silicon Success at Toshiba Memory
- Writing Sequences Tips
- Virtual Sequences
- Sequences 101
- Specman - 5 minutes on Methods Extensions
- Specman Temporal Options
- Specman Performance Enhancement
- Mahesh Soni, Specman Expert on Leveraging the Testcase Generation Utility
- Using the Specman Profiler
- Achieving Better-Quality Results with Specman Elite
- Verification expert tips for improving testbench quality with Specman
- Texas Instruments - Using the Perspec Solution
- The Palladium Solution and SoC Emulation for 16nm Automotive Devices at NXP
- Leveraging Specman for Signoff
- Leveraging Specman for Verification
- Specman Tips & Trick, e-HDL types compliance checks.
- Automotive Sensor Design Enablement
- HPE Apollo 70 Collaboration
- The Cadence vManager Metric-Driven Signoff Platform in Use at NXP
- Specman: Fastest Patches on Earth
- Specman Tips & Tricks: Save, Restart & Dynamic Load with Specman
- Orit Kirshenberg - Expert Insights Video
- New Cadence Products Expand the Verification Suite: Xcelium Parallel Simulator and Protium S1 Platform
- Reduce FPGA-Based Prototype Bring-Up From Months to Days with Cadence Protium S1 Platform
- Nadav Eden – Specman Expert Insights Video
- New Key Features of Xcelium for Advanced Mixed-Signal Verification
- Extoll - Dr. Niels Burkhardt—Specman Expert Insights video
- Yoav Lurie—Specman Expert Insights Video
- The People Behind Range Generated Field (RGF) - Specman 18.03
- Protium S1 used to prototype a pedestrian detection application.
- AMIQ Eclipse IDE for Perspec Portable Stimulus
- Mike Bartley, CEO of T&VS, on Portable Stimulus
- MultiPhy Verifies Diverse Blocks Quickly with Specman + MATLAB Flow
- ST Optimizes Verification Across the Globe with the vManager Platform
- Get Great Results with JasperGold CDC
- The Benefits of Running the Xcelium Parallel Logic Simulator on Cavium’s Arm Based ThunderX2
- Latest News for Cadence Specman Elite - January 2018
- Using the Cadence VirtualBridge Emulator with the Palladium Platform
- Taking FPGA-Based Prototyping to the Next Level
- Accellera Portable Stimulus Standard Introduction and Demo; Part 1 of 3 – Introduction
- Accellera Portable Stimulus Standard Introduction and Demo; Part 2 of 3 – The Demo
- Accellera Portable Stimulus Standard Introduction and Demo; Part 3 of 3 - Conclusions
- DAC 2017 Report on Accellera Portable Stimulus Specification
- Xcelium Parallel Simulator on Cavium Arm-based ThunderX2
- CDNLive India – A Closer Look at State-of-the-Art Verification Techniques and Methodologies
- New JasperGold platform for Advanced RTL Signoff
- Achieve Dramatic Speed-Up in Logic Simulation with Xcelium Parallel Simulator
- AMD - Cadence Palladium XP & In-Circuit Acceleration
- Open-Source UVM Multilanguage Architecture Simplifies Verification IP Reuse
- Augmenting Simulation Via Low-Power Verification Methodologies with Emulation
- Imperas Software - Cadence System Development Suite
- Finding Difficult Bugs Early Via Emulation
- Low-Power Mixed-Signal Verification of Freescale Kinetis Products
- UVM methodology based Verification Environment for Imaging IPs/SoCs
- Verifying Freescale's 64-bit Core with Rapid Prototyping Tools
- IBM - Cadence Functional Verification for Improved Planning and Schedule Adherence
- Closing Gaps in Mixed-Signal Power Implementation Using a Consistent Power Intent
- Formal Methodology as a 1st Step in Verification Shortens Process by 4 Weeks
- Xilinx - Cadence Virtual Processing Platform and Zynq-7000
- Increased Trace Depth, Faster Upload and Time to Market for Zenverge
- Validating Mobile SoC Architecture at Broadcom
- Palladium Z1: Advanced Job Re-shaping
- Accurate Low Power verification on a Complex Low Power Design using CLP
- LPDDR4 IP Verification Challenges
- DVCon 2013 Best Practices in Verification Planning
- DAC 2012: Interview with Dr. Kerstin Eder about her course on functional verification
- Cadence Perspec System Verifier SW Driven SoC Verification Automation
- Emulating Nvidia GPUs
- Pedestrian Detection: Cadence Tensilica IVP DSP on Cadence Protium FPGA-based prototyping platform
- Car window anti-trap protection with the Cadence Zynq-7000 Virtual Platform
- Freescale - Palladium XP helps speed their verification effort by 10,000x over simulation
- Get Your Weekends Back with Faster Chip Verification Process
- Dancing Robots! @CDNLive EMEA 2014
- NVIDIA Handles Complexity with Palladium Z1 Platform
- Metric-Driven Verification: A Look at How this Methodology Accelerates Verification Process
- Incisive vManager Solution - Experience the Difference
- See How Nvidia Boosts IP Acceleration of Custom ARM Core
- Cadence Functional Safety Solution
- Verify Smarter with Industry's First Datacenter-Class Emulation System
- Experiences with SoC Deployment of Hardware Emulation Based Power Intent Modeling
- Reducing Time to Point of Interest with Accelerated OS Boot
- One Metric to Rule Them All? Tracking Progress on Formal Testbenches
- Low Power Verification USING CPF/IEEE 1801 and Application of Formal Verification at Chip Level
- Next-Generation JasperGold Formal Verification Platform
- Big FPGA Boards for ASIC Prototyping
- Verification Solutions for ARM v7/v8 Based Systems on Chip
- Imagination - The Ten Myths about Formal
- Case Studies for Successful FPGA Based Prototyping
- Pre and Post Silicon Verification: The Best of Both Worlds
- Using Palladium Platform to Exhaustively Verify a Configurable Coherent NoC IP
- Delivering High Quality Denver IP Utilizing IP Acceleration
- Is End-to-End Formal Complete?
- JasperGold Formal Apps for Design Bring-up
- Enabling Verification of Complex System Scenarios Using Perspec System Verifer
- High-Level Synthesis: a Winning Technology
- Leveraging a System-C Based Design Flow
- NVIDIA - Palladium/VSP ARM v8 Tegra Hybrid
- X-FAB Revamps Low-Power Design Flow with CPF
- Introducing the Palladium Z1 Enterprise Emulation Platform
- PMC Expert Insights video
- 2X Productivity Gain Verifying DDR Controller Using Specman/e
- Tapping Into UVM-ML to Support Reuse in Multi-Language Verification Environment
- Achieving Fast Formal Verification in Highly Configurable Design Environment
- Faster HW/SW Verification and Bring-up with Hybrid Virtual Platform
- Detecting System-Level Corner Cases During Low-Power SoC Verification
- Detecting Low-Power Bugs with X-Optimism Simulation
- Fast Debug of RTL, Speedy Post Analysis
- Dialog Semiconductor Verifies Register Map Overnight with Cadence RegVal Formal App
- Freescale Tracks Thousands of Simulations Before Tapeout for Bug-Free Silicon
- Methods2Business Creates MAC Layers Without Compromising on Verification with C-to-Silicon Compiler
- NXP Shortens Verification Cycle for Smart Card SoC
- How Real Number Modeling Improves Functional Verification for Mixed-Signal SoCs
- Faster Simulation, Faster Builds at Freescale with Palladium XP Platform
- Using SystemC and HLS to Evaluate Co-Processor Architectures
- Faster HW/SW Debug, Embedded Software Development and System Validation
- Faster Debugging with X-Propagation Simulation and SimVision Debug
- Palladium XP Introduction
- In-Circuit Acceleration Demo Full Version
- Hitachi: Faster Bring Up with Protium Platform
- Low-Power Verification Using Conformal Low-Power
- Design Challenges in Developing Sub-Volt IP Designs for IoT Applications
- Introducing Low-power Verification RAK
- PMC - Power Estimation – An Evolving Science
- Allegro Microsystems Improves Efficiency and Productivity with Incisive vManager Solution
- Freescale Closes Coverage Gap in SoC Environments with Palladium XP Platform
- Bluespec Taps Into Rapid Prototyping Platform for Hybrid Prototyping
- Shorten Verification Time with Specman
- Easing Embedded Software Development for Complex SOCs
- MediaTek Gets High-Quality Smart Devices to Market Quickly with Palladium Platform
- Emulating a Dual-Port 10G/40G NIC on Palladium and RPP
- FPGA Prototyping Enables Rapid Development of Customizable Processors
- Using Palladium/VSP Hybrid to Accelerate SW Development
- Hardware Solutions for FPGA-Based Prototyping
- 5 Steps to Your First Power Shut-off (PSO) Verification
- A Look at Cadence System Development Tools
- Freescale Best Practice in Verification Planning
- Contemporary Verification Consultants e-asing your verification pains with IEEE 1647 & IES
- Broadcom Faster System Bring Up with an Embedded Test Bench on Palladium
- System Level Low Power Verification Using Palladium and CPF
- Better Verification Performance with Incisive Enterprise Simulator
- Texas Instruments - Highly Scalable Multicore ARM A15 Verification with Specman/e
- Cadence Palladium for SoC Performance Validation and Analysis
- Musings on Advanced Functional Verification with Specman/e in FPGA for Medical Devices
- Hardware Solutions for FPGA-based Prototyping
- UVM Multi-language with e, SystemVerilog, SystemC, C/C++
- Firmware Development and Pre-silicon Verification with FPGA-based Prototyping
- Connecting SystemVerilog Real Numbers and Verilog-AMS Nets
- FPGA-Prototyping of an Automotive Ethernet based Parking Assist System
- UVM SystemVerilog in a Multi-Language SoC World
- UVM-Acceleration, Assertions and Coverage demo
- Testing The Testbench
- Plan-Driven Low-Power Verification and Debugging at STMicroelectronics
- Accelerate Your Verification Debug with the Incisive Debug Analyzer
- Leveraging SystemVerilog Real Number Modeling
- National and Cadence Building a More Efficient Chip Design Flow
- Speed Verification Turnaround by Extending MDV to TLM
- Tuning Your UVM Environment for Maximum Performance
- Best Practices in Verification Planning
- SoC Static Power Verification with Encounter Conformal Low Power
Datasheet (43)
- Emulation Development Kit for Palladium Series Datasheet
- Memory Model Portfolio for Palladium Series Datasheet
- X1 Enterprise Prototyping Platform
- Protium S1 FPGA-Based Prototyping Platform
- Perspec System Verifier Datasheet
- SpeedBridge Adapter for USB 3.0/2.0/1.1 Devices
- SpeedBridge Adapter for PCIe 4.0 Datasheet
- VirtualBridge Adapter for PCI Express 2.0/3.0 Datasheet
- Xcelium Parallel Logic Simulation Datasheet
- Protium S1 Single-FPGA Board Datasheet
- vManager Metric-Driven Signoff Platform Datasheet
- Memory Model Portfolio for Palladium Series Datasheet
- Virtual JTAG Virtual JTAG Debug Interface Datasheet
- RocketSim Parallel Simulation Engine Datasheet
- Palladium Z1 Enterprise Emulation Platform Datasheet
- Embedded Software Debug App Datasheet
- Incisive Functional Safety Simulator Datasheet
- Cadence SpeedBridge Adapter for USB 2.0 Host Datasheet
- Cadence SpeedBridge Adapter for PCI Express 3.0 Datasheet
- Stratus High-Level Synthesis Datasheet
- Cadence SpeedBridge Adapter for Serial ATA (SATA) Datasheet
- SpeedBridge Adapter for USB 3.0 Devices Datasheet
- Protium FPGA-Based Prototyping Platform Datasheet
- Cynthesizer Solution Datasheet
- Cadence SpeedBridge Adapter for Ethernet Datasheet
- Incisive Verification Apps Datasheet
- Cadence Accelerated Verification IP for PCI Express Datasheet
- Cadence Virtual System Platform for the Xilinx Zynq-7000 All Programmable SoC Datasheet
- Incisive Enterprise Verifier Datasheet
- Incisive Enterprise Simulator Datasheet
- Cadence SpeedBridge Adapter for ARM Logic Tiles Datasheet
- Cadence Palladium Dynamic Power Analysis Datasheet
- Cadence Virtual System Platform Datasheet
- Cadence SpeedBridge Adapter for Serial-Attached SCSI (SAS) Datasheet
- Cadence SpeedBridge System for Video and Audio Datasheet
- Cadence Incisive SpeedBridge Adapter for PCI Express 2.0 Datasheet
- Cadence SpeedBridge Adapter for PCI Express Datasheet
- Incisive Assertion-Based Verification IP (ABVIP) for OCP Datasheet
- Incisive Formal Verifier Datasheet
White Paper (21)
- Improving Simulation Throughput Using Xcelium Parallel Logic Simulator
- Delivering Superior Throughput for EDA Verification Workloads White Paper
- Three Things You Need to Know to Use the Accellera PSS White Paper
- Efficient Verification of Mixed-Signal SerDes IP Using UVM
- Choosing the Right Verification Technology for CDC-Clean RTL Signoff
- Choosing the Right Superlinting Technology for Early RTL Code Signoff White Paper
- A Program Manager’s Guide to Successful Integrated Circuit Verification
- Massive SoC Designs Open Doors to New Era in Simulation White Paper
- SoC Planning, Management, Reporting, Auditing, and Signoff White Paper
- Improving Emulation Throughput for Multi-Project SoC Designs White Paper
- Gate-Level Simulation Methodology White Paper
- Automating Root-Cause Analysis to Reduce Time to Find Bugs by Up to 50% White Paper
- How the Productivity Advantages of High-Level Synthesis Can Improve IP Design, Verification, and Reuse White Paper
- Enabling ISO 26262 Qualification By Using Cadence Tools White Paper
- A Better Tool for Functional Verification of Low-Power Designs with IEEE 1801 UPF White Paper
- Meeting Functional Safety Requirements Efficiently Via Electronic Design Tools and Techniques White Paper
- Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components White Paper
- Productivity, Predictability, and Use-Model Versatility: The Three Key Care-Abouts of Choosing Hardware-Assisted Verification White Paper
- Building Energy-Efficient ICs from the Ground Up White Paper
- Solutions for Mixed-Signal SoC Verification White Paper
- Interface Additions to the e Language for Effective Communication with SystemC TLM 2.0 Models White Paper
Success Story Video (8)
- Xilinx - Cadence Virtual System Platform to Accelerate Product Development
- AMD - Cadence Palladium XP & In-Circuit Acceleration
- UVM methodology based Verification Environment for Imaging IPs/SoCs
- NVIDIA Handles Complexity with Palladium Z1 Platform
- See How Nvidia Boosts IP Acceleration of Custom ARM Core
- Introducing the Palladium Z1 Enterprise Emulation Platform
- Shorten Verification Time with Specman
- Plan-Driven Low-Power Verification and Debugging at STMicroelectronics
Technical Brief (4)
Press Releases (92)
- Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation
- ケイデンス、Portable Test and Stimulus Methodology and Libraryを発表
- Cadence Delivers Portable Test and Stimulus Methodology and Library
- ケイデンス、市場初のDisplayPort 2.0検証IPを発表
- ケイデンス、エンタープライズプロトタイピングシステム初の データセンター設置に最適化された拡張可能な新製品Protium X1を発表、 早期ソフトウェア開発を支援
- NVIDIA、ケイデンスの新製品Protium X1 Platformを採用し、 大規模GPUのソフトウェア開発を加速
- Cadence Launches Protium X1, the First Scalable, Data Center-Optimized Enterprise Prototyping System for Early Software Development
- NVIDIA Deploys the New Cadence Protium X1 Platform to Accelerate Software Development of Large-Capacity GPUs
- Thinci、AI設計にCadence Verification Suiteを採用し、 プロジェクトスケジュールを数か月加速
- Cadence Palladium and Protium Platforms Enable Innovium to Accelerate First-Pass Silicon Success for the Data Center Market
- ケイデンス、機械学習技術を活用した第三世代 JasperGold Formal Verification Platformを発表
- ケイデンス、業界初のUSB4向け検証IPを発表
- Arm, Cadence and Xilinx Introduce First Arm Neoverse System Development Platform for Next-Generation Cloud-to-Edge Infrastructure, Implemented on TSMC 7nm Process Technology
- ケイデンス、クラウドからエッジまでコンピューティングインフラ市場を前進させる Armの新しいNeoverse N1プラットフォーム向けにEDAツールおよびIPを最適化
- グローバルファウンドリーズ、プライマリEDAツールベンダーとしてケイデンスを採用
- Cadence Selected as Primary EDA Tool Vendor by GLOBALFOUNDRIES
- ケイデンス、シリコン製造開始前のArmベアメタルの コンプライアンステスト自動化により、Armベースサーバーの開発を加速
- Cadence Verification Suite、ArmベースHPCデータセンターに対応
- Cadence Verification Suite Enabled on Arm-Based HPC Datacenters
- Cadence Accelerates Arm-Based Server Development by Automating Arm Pre-Silicon Bare Metal Compliance Testing
- ケイデンスのPalladium Z1 Enterprise Emulation Platformが GUCのSoC設計を加速
- 日立、安全保護系コントローラの検証にJasperGoldを使用
- Cadence JasperGold Formal Verification Platform Enables Hitachi to Develop Measures for Fault Avoidance to Comply with IEC 61508 Series SIL 4 Requirements
- ケイデンス Perspec System Verifier、 Accellera Portable Test and Stimulus Specification 1.0に対応
- Cadence Perspec System Verifier Supports New Accellera Portable Test and Stimulus Specification 1.0
- ケイデンスのデジタル設計フルフロー、サインオフ、およびシステム機能検証製品群、7nm Arm Cortex-A76 CPUデザインに最適な結果を提供
- Cadence Full-Flow Digital and Signoff Tools and Verification Suite Provide Optimal Results for 7nm Arm Cortex-A76 CPU Designs
- ケイデンス、UFS 3.0、CoaXPress、およびHyperRAM向けの検証IP新製品を発表、車載向けSoCの検証収束までの期間を短縮
- ケイデンス、業界初のPCI Express 5.0検証IPの提供開始を発表
- ケイデンスとArm、低消費電力かつ高性能なArmサーバー上で起動する 初のSoC検証ソリューションを提供
- 広島大学、ケイデンスのTensilica Vision P6 DSPコアおよび Protium S1 FPGAベース プロトタイピングプラットフォームを活用し、 医療診断支援システムの開発を高速化
- ケイデンス、自動車機能安全規格ISO 26262認証機関TÜV SÜDより 業界初めて包括的な「TCL1適格」認定を取得
- テラダイン、ケイデンスのXcelium Parallel Logic Simulatorを 標準ツールとして採用
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
- Hiroshima University Research Team Accelerates the Development of a Computer-Aided Medical Diagnosis System with Cadence Tensilica Vision P6 DSP Core and Protium S1 FPGA-Based Prototyping Platform
- Teradyne Standardizes on Cadence Xcelium Parallel Logic Simulator
- ケイデンスのデジタル設計、サインオフおよびシステム機能検証ソフトウェア各製品群がArm Cortex-A75 CPU、Cortex-A55 CPU、Arm Mali-G72 GPUに対応
- ケイデンスPalladium Z1 Emulator向けにVirtualBridge Adapterを発表、ソフトウェアの立ち上げ期間を最大で3か月短縮
- Cadence Announces VirtualBridge Adapter for Palladium Z1 Emulator to Accelerate Software Bring-Up Time by Up to Three Months
- ケイデンス、フォーマル検証ベースのRTLサインオフ向けにJasperGoldプラットフォームを拡張
- Cadence Expands JasperGold Platform for Advanced Formal-Based RTL Signoff
- ケイデンスが業界初のCCIX向けインタフェースIPおよび検証IPのソリューションを発表、新しいクラスのデータセンターサーバーに対応
- Amlogic社、ケイデンスのProtium S1 FPGAベース・プロトタイピング検証プラットフォームを使用してマルチメディア向けSoCのハードウェア／ソフトウェア統合検証期間を２か月短縮
- Amlogic Reduces HW/SW Integration Time for Multimedia SoCs by Two Months Using the Cadence Protium S1 FPGA-Based Prototyping Platform
- ケイデンスのPerspec System Verifierを使用し、ルネサスがMCUの設計を加速
- Renesas Accelerates IoT Design Using the Cadence Perspec System Verifier
- ディジタルメディアプロフェッショナル、ケイデンスのPalladium XP検証コンピューティング・プラットフォームおよびHosted Design Solutionsを使用して開発期間を短縮
- ケイデンス、ソフトウェアの早期開発に向けてProtium S1 FPGAベース・プロトタイピング検証プラットフォームを発表
- ケイデンス、実製品への適用実績を持つ業界初の並列機能シミュレーターXcelium Parallel Simulatorを発表
- Cadence Launches Protium S1 FPGA-Based Prototyping Platform for Early Software Development
- Cadence Launches Xcelium Parallel Simulator, the Industry’s First Production-Proven Parallel Simulator
- Cavium社がケイデンス Palladium Z1エンタープライズ・エミュレーション・プラットフォームを採用
- ケイデンスのハードウェアエミュレータPalladium Z1開発チームが米国ACE (Annual Creativity in Electronics)アワードを受賞
- ケイデンス、自動車機能安全規格ISO 26262に対応する業界初の包括的なTCL1ドキュメントを提供
- 富士通、「ポスト京」スーパーコンピューター開発にケイデンスのPalladium Z1エンタープライズ・エミュレーションプラットフォームを採用
- Fujitsu Adopts Cadence Palladium Z1 Enterprise Emulation Platform for Post-K Supercomputer Development
- ドワンゴ、同社初のデータセンターサーバー向けカスタムハードウェアのアーキテクチャ開発にケイデンスのIncisive Enterprise Simulatorを採用
- ルネサス エレクトロニクス、ケイデンスのInterconnect Workbenchを採用し、オンチップインターコネクトのパフォーマンス解析および検証を加速
- ケイデンス、ARMとの協業を拡充し、設計工程全体をカバーする業界初のHosted Design SolutionによりカスタムSoC及びIoTシステム設計を加速
- 日立、ミックスシグナル設計検証向けにケイデンスのAMSモデルベース検証手法およびツール群を採用
- ケイデンス、ARMのCoretex-A73 CPUおよびMali-G71 GPUコア向け10nmリファレンスフローのRAK（Rapid Adoption Kits）を提供
- ケイデンス、Rocketick Technologies社の買収を完了
- Cadence Completes Acquisition of Rocketick Technologies
- ケイデンス、論理シミュレーションの画期的な並列高速化技術を提供するRocketick社を買収
- 先進運転支援システムのための交通標識認識システムの開発期間をプロトタイピング・プラットフォームにより70%削減
- ケイデンス、Palladium Z1 エンタープライズ・エミュレーションプラットフォームを発表、データセンタークラス・エミュレーションの新たな時代をリード
- Cadence Ushers in New Era of Datacenter-class Emulation with Palladium Z1 Enterprise Emulation Platform
- ケイデンス、ARM AMBA 5 AHB5向けの検証IPを発表
- Altair Semiconductor、最先端のIoT向けSoC開発にケイデンスのPalladium XPプラットフォームを採用
- Altair Semiconductor Adopts Cadence Palladium XP Platform for Advanced IoT SoC Development
- Realtek、ケイデンスのPalladium XPプラットフォームによりSoCの検証を加速
- Realtek Accelerates System-on-Chip Verification with Cadence Palladium XP Platform
- ケイデンス、次世代のフォーマル検証プラットフォームJasperGoldを発表
- Cadence Announces Next-Generation JasperGold Formal Verification Platform
- ケイデンス、デバッグにおける生産性を最大で50％向上させるIndago Debug Platformを発表
- Cadence Introduces Indago Debug Platform, Improving Debugging Productivity by up to 50 Percent
- Media Alert: Cadence to Showcase System Design and Verification Solutions at DVCon US 2015
- M31 Technology Adopts Cadence Verification IP to Achieve 2.5X Faster Verification
- DMPがケイデンスのPalladium XPプラットフォームを採用し、高性能グラフィックスIPコアの開発を加速
- DMP Adopts Cadence Palladium XP Platform to Accelerate High Performance Graphic IP Core Development
- ケイデンスのPerspec System Verifier、SoC検証の生産性を最大で10倍向上
- Sonics、オンチップのネットワークIP開発にケイデンスのJasperGold Appsフォーマル検証を採用
- ARMがケイデンスのPalladium XPプラットフォームとARM Fast Modelsの併用により、Mali GPUの開発でOS立ち上げ時間を50倍に高速化
- ケイデンスが、Protium ラピッド・プロトタイピング・プラットフォーム およびSystem Development Suiteの低消費電力検証の拡充を発表
- Cadence Announces Protium Rapid Prototyping Platform and Expands System Development Suite Low-Power Verification
- CSR、ARMベースの車載用インフォテイメント・システム開発向けにケイデンスのPalladium XPプラットフォームを選択
- ハイシリコン、モバイルやデジタルメディア向けシステム・オン・チップ(SoC)およびASIC開発用として、ケイデンスのPalladium XP プラットフォームの利用を拡大
- スプレッドトラム、モバイルSoCおよびハードウェア・ソフトウェア検証向けにケイデンスPalladium XP IIプラットフォームを採用
- ケイデンスのIncisive Specman Elite Testbench、シャープの検証期間を半減
- Cadence Incisive Specman Elite Testbench Reduces Verification Time for Sharp by 50 Percent
- Cadence Redefines Verification Planning and Management with Incisive vManager Solution
- Cadence Incisive 13.2 Platform Sets New Standard for SoC Verification Performance and Productivity
Customers Success (21)
- Valens and Cadence: Cadence Specman Elite Offers Vast Flexibility to Developers
- Renesas and Cadence: Building a State-of-the-Art Verification Environment Customer Success Story
- Renesas Deploys Cadence Interconnect Workbench with Palladium Z1 Platform
- Cadence and NetSpeed Success Story
- Moving to UVM-MS to Meet Coverage Goals Case Study
- Faster Hardware Verification and Software Validation for Supercomputers Success Story
- Cadence and VIA Telecom Success Story
- Cadence and Faraday Technology Case Study
- Cadence and STMicroelectronics Success Story
- Cadence and Melexis Success Story
- Cadence and STMicroelectronics Success Story
- Cadence and RivieraWaves Success Story
- Cadence and Siemens Healthcare Success Story
- Texas Instruments and Cadence Verification Success Story
- Cadence and Nufront Success Story
- Cadence and Samsung Success Story
- Cadence and STMicroelectronics Success Story
- Cadence and QLogic Success Story
- Cadence and Xilinx Success Story
- Cadence and Newport Media Success Story
- Cadence and UPEK Success Story
Webinar (20)
- Protium FPGA-Based Prototyping Platform
- Augmenting Simulation Via Low-Power Verification Methodologies with Emulation
- Metric-Driven Verification: A Look at How this Methodology Accelerates Verification Process
- 5 Steps to Your First Power Shut-off (PSO) Verification
- Better Verification Performance with Incisive Enterprise Simulator
- Connecting SystemVerilog Real Numbers and Verilog-AMS Nets
- Formal Apps to Automate Mainstream Verification Challenges
- Introducing UVM Multi-Language Open Architecture
- UVM SystemVerilog in a Multi-Language SoC World
- Verification Techniques with Assertion-Based VIP
- Optimizing Your Verification Process with Incisive vManager
- What to Do When Code Coverage Closure Seems Impossible
- Why Debug at Signal Level
- SimVision Simplifies UVM SystemVerilog Macro Debug
- Simplify UVM Debug with Cadence Incisive SimVision
- Accelerate Your Verification Debug with the Incisive Debug Analyzer
- Leveraging SystemVerilog Real Number Modeling
- Speed Verification Turnaround by Extending MDV to TLM
- Tuning Your UVM Environment for Maximum Performance
- Best Practices in Verification Planning
Demo (5)
- Accellera Portable Stimulus Standard Introduction and Demo; Part 1 of 3 – Introduction
- Accellera Portable Stimulus Standard Introduction and Demo; Part 2 of 3 – The Demo
- Accellera Portable Stimulus Standard Introduction and Demo; Part 3 of 3 - Conclusions
- Xcelium Parallel Simulator on Cavium Arm-based ThunderX2
- FPGA-Prototyping of an Automotive Ethernet based Parking Assist System
Customers
The Palladium Z1 platform uniquely met our requirements due to its reliability as a datacenter compute resource, offering advanced multi-user capabilities and scalability from small four-million-gate verification payloads to multi-billion gate designs.
Daniel Diao, Deputy General Manager of the Turing Processor Business Unit, Huawei
The ability to use the same bring-up flow for Palladium emulation and Protium rapid prototyping allows our design teams to switch seamlessly between the two execution engines, which reduces the prototype bring-up time from months to weeks.
Hideya Sato, Deputy Executive GM, Hitachi, LTD
The vManager platform has been very well accepted by our design and verification teams because it’s really straightforward, intuitive, and easy to use. The vManager platform helps us with project visibility, which improves our verification productivity.
Mirella Negro Marcigaglia, Verification Manager, STMicroelectronics
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