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    • デジタル設計/サインオフ
      デジタル設計/サインオフ 概要

      Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

      Full-Flow Digital Solution Related Products A-Z

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        • Genus Synthesis Solution
        • Virtuoso Digital Implementation
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      • SDC and CDC Signoff
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        • Voltus-Fi Custom Power Integrity Solution
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        • Modus DFT Software Solution
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        • 3D-IC設計ソリューション
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        • Low Power設計ソリューション
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    • カスタムIC/アナログ/RF設計
      カスタムIC/アナログ/RF設計概要

      Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

      概要 Related Products A-Z

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      • 回路設計
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        • What's New in Virtuoso
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      • ライブラリ・キャラクタライゼーション
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        • Liberate Trio Characterization Suite
        • Virtuoso Liberate MX Memory Characterization Solution
        • Virtuoso Liberate AMS Mixed-Signal Characterization Solution
        • Liberate Variety Statistical Characterization
        • Liberate Characterization Solution
        • Liberate LV Library Validation Solution
      • レイアウト設計
        • Flows/Tools
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        • Legato Memory Solution
        • Legato Reliability Solution
        • 5G Systems and Subsystems
    • システム設計/検証
      システム設計/検証 概要

      Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

      Verification Suite Related Products A-Z

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        • vManager Metric-Driven Signoff Platform
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        • Xcelium Parallel Simulator
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    • IP
      IP 概要

      An open IP platform for you to customize your app-driven SoC design.

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      • Analog IP
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    • ICパッケージ設計/解析
      ICパッケージ設計/解析 概要

      Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

      概要 Related Products A-Z

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      • ICパッケージ設計
        • Flows/Tools
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        • SiP Digital Architect
      • ICパッケージ向けSI/PI解析ソリューション
        • Flows/Tools
        • Allegro Sigrity SI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity Serial Link Analysis Option
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        • Allegro Sigrity PI Base
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI解析ツール
        • Flows/Tools
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        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity XtractIM
        • Sigrity XcitePI Extraction
      • IC/パッケージ/ボード協調設計・検証
        • Flows/Tools
        • OrbitIO Interconnect Designer
        • IO-SSO Analysis Suite
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        • Sigrityテクノロジー最新情報
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    • SYSTEM INNOVATION
    • システム解析
      システム解析概要

      Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

      Overview Related Products A-Z

      製品カテゴリー
      • Electromagnetic Solutions
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    • PCB設計/解析
      PCB 設計/解析概要

      Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

      概要 Related Products A-Z Service Bureaus

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      • 回路設計
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      • プリント基板レイアウト
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        • Allegro EDM Solution
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      • アナログ/ミックスシグナル・シミュレーション
        • Flows/Tools
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      • PCB設計向けSI/PI解析ソリューション
        • Flows/Tools
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity SI Base
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        • Allegro Sigrity Power-Aware SI Option
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      • SI/PI解析ツール
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      • Allegro最新情報
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  • Power-Aware Signal Integrity Analysis

Power-Aware Signal Integrity Analysis

完全なDDR4とLPDDR4のパワー・アウェアなSI ソリューション

Addressing the “Power-Aware” Challenges of Memory Interface Designs

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Key Benefits

  • 反射、損失、クロストーク、およびSSO効果を同時シミュレーションが可能
  • パワー・アウェアなトランジスタからビヘイビアへのI/Oモデル作成を提供
  • 測定用波形の包括的なJEDECベースのポスト・プロセッシング機能

パワー・アウェアなシグナル・インテグリティ解析とは? 一部のツールは、消費電力を意識したI/Oモデリング規格のみをサポートしますが、Cadence® Sigrity™テクノロジーはそれだけではありません。 次の要件を満たすお手伝いをいたします:

  • チップ、パッケージ、およびPCB間のカップル信号、パワー、およびグランドの正確な抽出
  • パワー・アウェアなIBISモデルの作成と読み取り
  • 最新のメモリーインターフェースとビット・エラー・レート(BER)に関するJEDEC仕様

トランジスタレベルのモデルをパワー・アウェアなIBISモデルに変換

Sigrity™ Transistor-to-Behavioral Model Conversion(T2B™)は、IBISモデルをトランジスタからビヘイビアに変換することで、正確で効率的なパワー・アウェアなバス・シミュレーションを、トランジスタレベルのモデルで要する時間を日数レベルではなく数時間で実現します。

ICのパワーおよびグラウンドに結合されたICの再配線層の信号を正確にモデル化

Sigrity XcitePI™ Extractionは、I/Oからバンプまでの信号パワーとグランドインターコネクトをチップレベルで抽出し、ヘッダー情報を使用して抽出されたパッケージモデルへのプッシュボタン接続を可能にします。 

フルウェーブ3Dとハイブリッドソルバー・テクノロジーを融合したフルパッケージ・モデリング

Sigrity XtractIM™テクノロジーと3D-EMテクノロジーは、信号タイプ、電源、およびグランドの相互接続モデルを結合するために、パッケージタイプに関係なく、完全なパッケージモデルを作成するために連携して動作します。 パッケージのデザイナーとパッケージアセスメントのエンジニア間のギャップを埋めるパッケージのアセスメントも含まれています。

PCBの高速で正確な電気モデリング

Sigrity PowerSI™テクノロジーは、PCBのカップル信号、パワーおよびグランドを抽出します。抽出したモデルには、抽出したパッケージモデルやコネクタモデルへのプッシュボタン接続を可能にするヘッダー情報が含まれています。

DDRおよびLPDDRインターフェースのスピーディーな探索と検証

Sigrity SystemSI™テクノロジーは、パワー・アウェアなIBIS モデルとパワー・アウェアなインターコネクトモデルの容易なコネクティビティにを提供します。シミュレーションの結果は、ワーストケースの条件を徹底的に決定し、それらの結果を JEDEC のコンプライアンス要件と比較して、BER の要件を含む DDR4 インターフェースのサインオフが可能です。

機能

  • 使いやすいブロックレベルのスケマティック環境
  • 大規模なインターコネクト構造の効率的な S パラメータ抽出のためのハイブリッドソルバー
  • 高周波構造の詳細抽出のための3Dフルウェーブソルバー
  • Sパラメータのチューニング、チェック、およびブロードバンドSPICE モデル変換
Additional Resources:
  • Power-Aware SI DDR4 Simulation
  • Why Does Signal Integrity Analysis Need to be Power Aware?
  • Designing Data Bus with DDR5 Technology

Why You Need a Complete DDR4 Power-Aware SI Solution

  • Related Products

    • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
    • Sigrity XtractIM
    • Sigrity XcitePI Extraction
    • Sigrity PowerSI
    • Sigrity SystemSI
  • Related Information

    • Power-Aware SI DDR4 Simulation: You Have a Choice!
    • Why Does Signal Integrity Need to Be Power Aware?
    • Designing Data Bus with DDR Technology
Videos

Sigrity Tech Tip: How DDR interfaces can be accurately analyzed pain-free (without large S-parameters)

DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques

SiriusXM Simulates DDR3 Interfaces with Sigrity Tools

Sigrity Tech Tip: How to Find Signal Integrity Problems on an Unrouted PCB

Nexus Interposers and Cadence Tools Enhance DDRx Designs

Sigrity Tech Tip: How PCB Designers Can Jumpstart Electrical Signoff Using Power-Aware Rule Checks

News ReleasesVIEW ALL
  • Cadence DesignTrue DFM Ecosystem Connects Manufacturers with Customers to Ensure PCB Design Manufacturability Early in the Design Process 09/04/2018

  • Cadence Introduces Voltus-XP Technology with Extensive Parallelism, Up to 5X Acceleration, and Increased Capacity for Power Signoff at Advanced Nodes 07/23/2018

  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis 07/19/2018

  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability 03/19/2018

  • ケイデンスの新製品Allegro PCB DesignTrue DFMテクノロジが新規製品開発と導入プロセスを加速 09/13/2017

BlogsVIEW ALL
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