The Cadence® IP for 10Gbps Multi-Protocol PHY simplifies the design process without compromising performance, power, or silicon die area. Crafted for mobile, wireless IoT, consumer, and automotive designs, the IP is designed for multi-protocols running on a single PHY macro and is compliant with USB 3.1, PCI Express® (PCIe®) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, 10G-KR and QSGMII/SGMII.
Multi-Protocol with Multi-Link Capability
Single PHY macro offers optimum SoC configurability with the protocol mix and match
Optimized Performance, Power, and Area
Best fit for applications requiring performance with small footprint
Comprehensive Test Feature Enable Rapid SoC Development
Extensive BIST and DFT enable ease of integration, faster bring-up, and quick debugging