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    • デジタル設計/サインオフ
      デジタル設計/サインオフ 概要

      Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

      Full-Flow Digital Solution Related Products A-Z

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      • 等価性検証
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        • Genus Synthesis Solution
        • Virtuoso Digital Implementation
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      • SDC and CDC Signoff
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        • Voltus-Fi Custom Power Integrity Solution
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        • 3D-IC設計ソリューション
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        • Low Power設計ソリューション
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    • カスタムIC/アナログ/RF設計
      カスタムIC/アナログ/RF設計概要

      Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

      概要 Related Products A-Z

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      • 回路設計
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        • What's New in Virtuoso
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        • Spectre Simulation Platform
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      • ライブラリ・キャラクタライゼーション
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        • Liberate Trio Characterization Suite
        • Virtuoso Liberate MX Memory Characterization Solution
        • Virtuoso Liberate AMS Mixed-Signal Characterization Solution
        • Liberate Variety Statistical Characterization
        • Liberate Characterization Solution
        • Liberate LV Library Validation Solution
      • レイアウト設計
        • Flows/Tools
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        • 5G Systems and Subsystems
    • システム設計/検証
      システム設計/検証 概要

      Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

      Verification Suite Related Products A-Z

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        • vManager Metric-Driven Signoff Platform
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    • IP
      IP 概要

      An open IP platform for you to customize your app-driven SoC design.

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      • Analog IP
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    • ICパッケージ設計/解析
      ICパッケージ設計/解析 概要

      Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

      概要 Related Products A-Z

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      • ICパッケージ設計
        • Flows/Tools
        • Allegro Package Designer
        • SiP Digital Architect
      • ICパッケージ向けSI/PI解析ソリューション
        • Flows/Tools
        • Allegro Sigrity SI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity Package Assessment and Extraction Option
        • Allegro Sigrity PI Base
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI解析ツール
        • Flows/Tools
        • Sigrity PowerSI
        • Sigrity PowerDC
        • Sigrity OptimizePI
        • Sigrity System Explorer
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        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity XtractIM
        • Sigrity XcitePI Extraction
      • IC/パッケージ/ボード協調設計・検証
        • Flows/Tools
        • OrbitIO Interconnect Designer
        • IO-SSO Analysis Suite
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        • IC/パッケージ/ボード協調設計ソリューション
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        • Sigrityテクノロジー最新情報
        • Virtuosoとの統合設計環境
        • PDN(power delivery network)設計
    • SYSTEM INNOVATION
    • システム解析
      システム解析概要

      Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

      Overview Related Products A-Z

      製品カテゴリー
      • Electromagnetic Solutions
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        • Clarity 3D Solver
        • Sigrity XcitePI Extraction
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    • FPGAプロトタイピング
    • PCB設計/解析
      PCB 設計/解析概要

      Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

      概要 Related Products A-Z Service Bureaus

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      • 回路設計
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        • Allegro Design Entry Capture/Capture CIS
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      • プリント基板レイアウト
        • Flows/Tools
        • Allegro PCB Designer
        • OrCAD PCB Designer(外部サイト)
      • ライブラリ/設計データ管理
        • Flows/Tools
        • Electrical CAD-Mechanical CAD Library Creator
        • Allegro EDM Solution
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        • Allegro Pulse
      • アナログ/ミックスシグナル・シミュレーション
        • Flows/Tools
        • Allegro PSpice Simulator
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      • PCB設計向けSI/PI解析ソリューション
        • Flows/Tools
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity SI Base
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        • Allegro Sigrity Power-Aware SI Option
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      • SI/PI解析ツール
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      • Allegro最新情報
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  • Sigrity SystemSI

Sigrity SystemSI

一般的なトポロジーと標準インターフェースをすばやく実装

Sigrity SystemSI データシート

Backchannel Modeling and Simulation Using IBIS Standard Enhancements White Paper

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Key Benefits

  • 潜在的な問題を早期に特定し、コストと時間を削減
  • DCから> 56GHzまでのシリアルおよびパラレルリンクの統計的および時間/周波ドメイン解析
  • 関連するケイデンス・ツールでサポートされているシンプルなブロックベースの回路図エディタ

Cadence® Sigrity™ SystemSI™ テクノロジーは、一般的なトポロジーと標準インターフェースを迅速に実装するために、自動die-to-dieのシグナル・インテグリティ解析を2つの構成で実行します: SerDesチャネルに重点を置いて、パラレルバスとシリアルリンクのソース同期。 DCを56GHz以上にまでカバーするSystemSIテクノロジーは、周波数領域、時間領域、および統計解析手法を使用しています。どちらの構成も、汎用トポロジーの探索ツールで拡張されています。

Sigrity SystemSIは、次のインターフェースの設計を加速するために3つの主要機能を備えています。

Sigrity System Explorer

この汎用トポロジー探究ツールは、シグナル・インテグリティまたは過渡パワー・インテグリティ解析を一緒に実行できるようにすることを含め、エンドツーエンドのシグナルおよびパワートポロジーの探究に最適です。また、複雑なインターコネクトモデルを組み込み、相互接続モデルの各ポートの回路を自動的に複製する単一のドライバー/レシーバー/ディスクリート・シンボルに接続することもできます。

Sigrity SystemSI Parallel Bus Analysis

このエンドツーエンドの解析ソリューションは、DDRxメモリを使用した設計などのソース同期パラレルインタフェースをターゲットにしています。プリレイアウト機能(viaウィザードを含む)により、素早く生成され、接続されたモデルから始めることができます。設計が洗練されるにつれて、実際のハードウェアの動作を反映するために、より詳細なモデルを交換することができます。並行シミュレーションは、誘電体損失、導体損失、反射、シンボル間干渉(ISI)、クロストーク、及び同時スイッチングノイズの影響を考慮します。これらのシミュレーションは、非理想的な電力供給システムの影響を十分に説明することができます。グラフィカルな出力とポストプロセスオプションにより、システムの迅速な改善が得られます。

Sigrity SystemSI Serial Link Analysis

賞を受賞したチップツーチップ解析ソリューションは、PCIExpress® (PCIe®)、HDMI、SFP +、Xaui、Infiniband、SAS、SATA、USBなどの高速SerDesデザインに焦点を当て、基本的なテンプレートを使用した早期評価を行います。 業界標準のIBIS AMIトランスミッタおよびレシーバモデルのサポートにより、複数のサプライヤのチップとのシリアルリンクのチャネル動作のシミュレーションを実行できます。チップモデルの開発者は、IBIS-AMIモデル開発を支援するテクニックにアクセスすることができます。複数のパッケージ、コネクタ、ボードのモデルを追加して、チャネル全体を反映させることができます。シミュレーションはクロストークの問題を特定し、チップレベルのクロックとデータ回復(CDR)技術の有効性を示します。数百万ビットのデータを含むフルチャネル・シミュレーションでは、ジッタおよびノイズ・レベルが指定された許容値内にあるかどうかを判断するために全体的なビットエラー率(BER)が確認されます。

 



Sigrity SystemSIは、環境への取り組みを容易にするために、ブロックベース回路エディタで始まり、非常に基本的なデータを簡単に使い始めることができます。 設計作業が進むにつれて、モデルがスワップインされ、設計構造の詳細が反映されます。

Features

  • 非理想的なパワー供給システムが SI に与える影響を的確に処理
  • 損失、反射、クロストーク、同時スイッチング出力 (SSO) などの SI 効果を同時に評価
  • 業界標準のIBIS AMI トランスミッタおよびレシーバモデルのサポートにより、複数のサプライヤからのチップを使用したシリアルリンクのチャネル動作のシミュレーション
  • 高度に自動化された計測/レポート機能

Learn how Avera Semi, a subsidiary of GLOBALFOUNDRIES, improved signal analysis for their LPDDR4 interfaces on MCM packages using Cadence Sigrity tools.

  • Related Information

    • Top 10 Reasons Real Signal Integrity Engineers Demand Power-Aware SI Technology
  • Related Products

    • Sigrity SPEED2000
    • Sigrity PowerSI
    • Sigrity PowerSI 3D EM Extraction Option
    • Allegro Sigrity Power-Aware SI Option
    • Allegro Sigrity Serial Link Analysis Option
Resource Library VIEW ALL

Conference Paper (10)

  • IBIS-AMI and Statistical Analysis Conference Presentation
  • Baseband IC Design Kits for Rapid System Realization
  • Accurate Modelling of PCIe 3.0 Analog Buffers Conference Paper
  • Bridging the Measurement and Simulation Gap Conference Paper
  • Model Extraction and Circuit Simulation Approaches for Successful SSO Analysis of Chip-Package-Board Systems Conference Paper
  • The Application of IBIS-AMI Model Cascaded Simulation for 10 Gigabit Repeater Serial Link Analysis Conference Presentation
  • AMI Simulation with Error Correction to Enhance BER Conference Paper
  • AMI Simulation with Error Correction to Enhance BER Performance Conference Presentation
  • IBIS–AMI Modeling Recommendations Conference Presentation
  • Panel Session TP-TU3 High-speed Channel Designs IBIS AMI Solution Conference Presentation

Video (5)

  • Cadence Solves the Challenges Faced by Mobiveil Technologies Hardware Group
  • Seagate Uses Cadence Allegro and Sigrity PCB Tools to Develop Next-Generation Solid-State Drives
  • DesignCon 2017: Sigrity 2017 Portfolio Highlights
  • Sigrity Tech Tip: How to Build an IBIS-AMI Model
  • Sigrity Tech Tip: How DDR interfaces can be accurately analyzed pain-free (without large S-parameters)

White Paper (2)

  • Backchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard White Paper
  • Power-Aware Analysis Solution Whitepaper

Article (1)

  • Signal Integrity

Press Releases (9)

  • Cadence 3D-IC Advanced Packaging Integration Flow Certified by Samsung Foundry for its 7LPP Process Technology
  • Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology
  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis
  • Cadence Supports New TSMC WoW Advanced Packaging Technology
  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability
  • Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff
  • Cadence Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces
  • Cadence and Spreadtrum Collaborate on Virtual Reference Design Kit to Reduce Customers' Design Cycle by Up to 12 Weeks
  • Cadence Expands Sigrity 2015 Technology Portfolio with New Products, a Key Feature Update and Flexible Licensing Options

Presentation (3)

  • Learn How to Turn Simulation into Reality for PAM4 Analysis Presentation
  • How to Efficiently Analyze a DDR4 Interface
  • Model Extraction and Circuit Simulation Approaches for Successful SSO Analysis of Chip-Package-Board Systems Presentation

Technical Brief (1)

  • Addressing the “Power-Aware” Challenges of Memory Interface Designs Technical Paper

Success Story Video (1)

  • Seagate Uses Cadence Allegro and Sigrity PCB Tools to Develop Next-Generation Solid-State Drives
Videos

Simulation of the Automotive Ethernet using Cadence Sigrity tools

GLOBALFOUNDRIES: MCM LPDDR4 Analysis Accelerates Turnaround Time by 12X Using Sigrity SystemSI

Ericsson Meets DDR and PCIe Specs While Avoiding Crosstalk

Why does signal integrity analysis need to be power-aware

Sigrity Tech Tip: How to Build an IBIS-AMI Model

Cadence Solves the Challenges Faced by Mobiveil Technologies Hardware Group

Sigrity Tech Tip: How DDR interfaces can be accurately analyzed pain-free (without large S-parameters)

DesignCon 2017: Sigrity 2017 Portfolio Highlights

Seagate Uses Cadence Allegro and Sigrity PCB Tools to Develop Next-Generation Solid-State Drives

News ReleasesVIEW ALL
  • Cadence 3D-IC Advanced Packaging Integration Flow Certified by Samsung Foundry for its 7LPP Process Technology 10/17/2019

  • Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology 04/23/2019

  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis 07/19/2018

  • Cadence Supports New TSMC WoW Advanced Packaging Technology 05/01/2018

  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability 03/19/2018

BlogsVIEW ALL
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