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    • デジタル設計/サインオフ
      デジタル設計/サインオフ 概要

      Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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    • カスタムIC/アナログ/RF設計
      カスタムIC/アナログ/RF設計概要

      Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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      • 回路設計
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        • Liberate LV Library Validation Solution
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    • システム設計/検証
      システム設計/検証 概要

      Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

      Verification Suite Related Products A-Z

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      IP 概要

      An open IP platform for you to customize your app-driven SoC design.

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    • ICパッケージ設計/解析
      ICパッケージ設計/解析 概要

      Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

      概要 Related Products A-Z

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      • ICパッケージ設計
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      • ICパッケージ向けSI/PI解析ソリューション
        • Flows/Tools
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      • SI/PI解析ツール
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      • IC/パッケージ/ボード協調設計・検証
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    • SYSTEM INNOVATION
    • システム解析
      システム解析概要

      Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

      Overview Related Products A-Z

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    • PCB設計/解析
      PCB 設計/解析概要

      Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

      概要 Related Products A-Z Service Bureaus

      製品カテゴリー
      • 回路設計
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      • プリント基板レイアウト
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      • PCB設計向けSI/PI解析ソリューション
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      • Allegro最新情報
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  • Sigrity PowerSI 3D EM Extraction Option

Sigrity PowerSI 3D EM Extraction Option

ICパッケージとPCBのパワー・インテグリティとシグナル・インテグリティ解析の高速化

Sigrity PowerSI 3D EM Extraction Option データシート

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Key Benefits

  • 複雑な3D構造に対応する高速で正確なEMソリューション
  • ワークフロー・ドリブンのユースモデル
  • スタックアップとマテリアルプロパティの表示と改良

ICパッケージとPCBのパワー・インテグリティとシグナル・インテグリティ解析、電磁界インタフェース(EMI)/電磁適合性(EMC)解析を加速するため、Cadence® Sigrity™ PowerSI® 3D EM Extraction Optionの3次元(3D)フルウェーブおよび準静電磁(EM)フィールドソルバは、モデル削減テクノロジーを使用してSパラメータモデル抽出を行います。複雑な3D構造の精度を目的とする、クラウド対応のツールは適応型有限要素メッシュ(FEM)リファインメント・テクノロジーを備えています。

3D有限要素メッシュ



左デザインの標準2Dビューは、ネットを選択し、個々のネットまたはネットグループを表示することを可能にします。 提供ワークフローの手順を進めることで、一般的なタスクの流れを繰り返し実行することができます。 右デザインの3Dビューでは、ビアを通した接続を追跡し、2Dビューのみでは不可能な相互接続の関係を視覚化することができます。

PowerSI 3DEM optionは3D 電磁解析のための3d ソリッドモデルを作成、編集、およびインポートするための3DメカニカルCAD GUI を内蔵しています。Acis、IGES、STEPのような一般的なMCADフォーマットだけでなく、Cadence Allegro®とSigrityのフォーマットから設計データを取り込むことができます。3Dメカニカルコンポーネントは、パラメータ化と数式で簡単に作成がすることができ、モデリングの柔軟性とシミュレーションの最適化を可能にします。

他の多くの機能と並んで、PowerSI 3DEM optionは、時間領域の過渡解析に使用するモデルを作成し、low-frequency-conditioningアルゴリズムのおかげで、100Hzまでの安定した正確なソリューションを提供します。PowerSI 3DEMオプションには、ワークフロー・ドリブンのユーザーインターフェイスとコンポーネントベースの自動ポート生成とグループ化があり、比較的簡単に使用できます。

準静的な抽出は、フルウェーブ・テクノロジーよりもはるかに高速に実行されますが、しかし、特定の仮定 (すなわち、電気と磁場が互いに独立している) になります。抵抗 (R)、インダクタンス (L)、キャパシタンス (C)、コンダクタンス (G) で構成される相互接続モデルの結果をすばやく生成します。

機能

  • 他の一般的な 3D FEM ツールよりも高速
  • 不均一基板を考慮したファイバーウェーブ・ウィザード
  • 周波数依存材料のサポート
  • 表面粗さ金属厚さ
  • 製造設計のためのパラメトリックスイープ (DFM)
  • 3Dメカニカルモデルを簡単に作成、編集、インポート
  • スタックアップと材料特性の表示と絞り込み
  • Cadence Allegro Sigrity SI/PI baseから直接起動を含むCadence SiP Layout, Allegro® Package Designer, およびAllegro PCB Designerを伴ったフロー向けに最適化
  • ケイデンス、メンター、または図研パッケージデータベースで容易に使用可能
  • Related Products

    • Allegro Sigrity Power-Aware SI Option
    • Allegro Sigrity Serial Link Analysis Option
    • Allegro Sigrity PI Signoff and Optimization Option
    • Allegro Sigrity Package Assessment and Extraction Option
Resource Library VIEW ALL

Press Releases (8)

  • Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology
  • Cadence Supports New TSMC WoW Advanced Packaging Technology
  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability
  • Cadence Delivers Design and Analysis Flow Enhancements for TSMC InFO and CoWoS® 3D Packaging Technologies
  • Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff
  • Cadence Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces
  • Cadence and Spreadtrum Collaborate on Virtual Reference Design Kit to Reduce Customers' Design Cycle by Up to 12 Weeks
  • Cadence Expands Sigrity 2015 Technology Portfolio with New Products, a Key Feature Update and Flexible Licensing Options

Conference Paper (4)

  • A Resonance-Free Power Delivery System Design Methodology Applying 3D Optimized Extended Adaptive Voltage Positioning Conference Presentation
  • Timing Skew Enabler Induced by Fiber Weave Effect in High Speed HDMI Conference Paper
  • Efficient Methodology for Modeling Structure of High-Speed Long Transmission Lines Conference Paper
  • Baseband IC Design Kits for Rapid System Realization

Success Story Video (2)

  • Seagate Uses Cadence Allegro and Sigrity PCB Tools to Develop Next-Generation Solid-State Drives
  • Lattice Saves Millions, Avoids Respins and Product Delays with Sigrity Tools

Video (5)

  • Seagate Uses Cadence Allegro and Sigrity PCB Tools to Develop Next-Generation Solid-State Drives
  • Sigrity Tech Tip: How to Accelerate Accurate 3D Full Wave Extraction Time
  • DesignCon 2015: Sigrity 2015 Portfolio Highlights
  • Sigrity Tech Tip: How to Build Accurate Leadframe Package Models Quickly and Easily
  • Lattice Saves Millions, Avoids Respins and Product Delays with Sigrity Tools

Presentation (2)

  • Learn How to Turn Simulation into Reality for PAM4 Analysis Presentation
  • How to Efficiently Analyze a DDR4 Interface

White Paper (1)

  • Save Time and Minimize Errors by Automating Co-Design and Co-Analysis of Chips, Boards, and Packages
News ReleasesVIEW ALL
  • Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff 01/25/2017

  • Cadence Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces 01/19/2016

  • Cadence and Spreadtrum Collaborate on Virtual Reference Design Kit to Reduce Customers' Design Cycle by Up to 12 Weeks 12/01/2015

  • Cadence Expands Sigrity 2015 Technology Portfolio with New Products, a Key Feature Update and Flexible Licensing Options 01/26/2015

BlogsVIEW ALL
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