Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview
- Provides 10X-100X the single-thread performance (10X over Spectre Circuit Simulator) with out-of-box SPICE accuracy and convergence
- Enables high-precision simulation for large, post-layout analog designs and subsystems without compromising accuracy
- Delivers scalable performance with a multi-core architecture, allowing higher levels of analog design integration and verification
- Uses foundry-certified device models (common across all simulation engines in the Virtuoso Multi-Mode Simulation solution) to ensure silicon-accurate analog designs
- TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements
The Cadence® Spectre® Accelerated Parallel Simulator provides scalable performance and capacity—at full Spectre Circuit Simulator accuracy—for complex analog, RF, and mixed-signal blocks and subsystems with tens of thousands of devices.
The Spectre Accelerated Parallel Simulator performs advanced SPICE-accurate simulation with faster convergence, scalable performance, and higher capacity. It is tightly integrated with the Cadence Virtuoso® custom IC design platform, allowing engineers to capture and pass design intent into the simulation environment, and it provides all the transistor-level analysis capabilities of the Spectre Circuit Simulator.
The proprietary full-matrix solving technology in the Spectre Accelerated Parallel Simulator delivers unparalleled scalability and multi-threading capability using modern multi-core compute platforms. These features and more ensure precise simulation without sacrificing accuracy of results.
Automotive TCL1 Certified for ISO 26262
The industry’s first analog/mixed-signal design implementation and verification flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The analog/mixed-signal design implementation and verification flow brings transistor-level designs from creation and simulation through physical implementation and verification using the Virtuoso ADE Product Suite and the Spectre Circuit Simulation Platform. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.
Press Releases (9)
- ケイデンス、TSMCと協業、7nm FinFET Plus設計の技術革新を加速
- Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation
- ケイデンス、業界初のメモリー設計・検証向け統合ソリューション、Legato Memory Solutionを発表
- Cadence Announces Legato Memory Solution, Industry’s First Integrated Memory Design and Verification Solution
- Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production
- Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry
- TSMC Adopts Cadence Solutions for 16nm FinFET Library Characterization
- ARM Implements the Cadence Library Characterization Solution for Advanced Node Foundation IP Development
- Cadence Characterization Solution for Complex Multi-bit Cells Delivers Power and Performance Benefits for Yamaha
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview