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- A built-in interconnect parasitic extraction engine rapidly evaluates layout as it is created and provides an in-design electrical view for real-time analysis and optimization
- EM analysis alerts layout engineers to any EM issues created as the layout is drawn
- Partial layout re-simulation helps prevent errors getting buried deep in a packed layout, minimizing respins and reducing the need to over design
Silicon advances have no doubt created new opportunities for product differentiation, but not without some unpredictability and uncertainty. Often, schematic creation (electrical), layout (physical), and verification steps are performed sequentially, with little or no visibility into the consequences of each physical design decision.
Cadence’s electrically aware design flow presents a substantial shift, where electrical analysis and verification move forward in the design process to provide verification in-design. Our flow provides incremental design analysis that includes accurate parasitic extraction of interconnect and device parasitics, electromigration (EM), and IR drop.
Using our flow, you can assess physical and electrical consequences of design decisions while these decisions are being made. Based on what you’ve observed, you can rerun simulation at any time with the layout parasitics, perform checks against performance-related constraints, and graphically evaluate pre- and post-layout waveforms. You can apply what-if analysis and in-design optimization across corners, which eliminates uncertainty that contributes to conservative overdesign.
You won’t have to worry about lag or interruptions because analysis and checking results are updated to your screen right away. As your design progresses, parasitic and current-related constraints are easily enabled and checked within your layout environment.
A key component of our electrically aware design flow is the Cadence Virtuoso® Layout Suite for Electrically Aware Design (EAD). The tool lets design teams monitor electrical issues while a layout is created, rather than waiting until the layout is completed before verifying that it meets the original design intent. You can electrically analyze, simulate, and verify interconnect decisions in real time to generate a layout that is electrically correct by construction.
Cadence’s electrically aware design flow, based on the Virtuoso Layout Suite for EAD, provides continual electrical checking and verification between circuit and layout design
|Layout Designer||Circuit Designer|
Receive immediate feedback on how a layout feature or change will impact design requirements as you draw the layout
Run "partial layout resimulation" to ensure that interconnect parasitics are not harming circuit performance
Discover EM issues as you're drawing the layout, and avoid problems immediately instead of waiting for a post-layout extraction
|Set electrical constraints (like matched resistance or capacitance) and pass these along to layout designers, who will receive instant feedback on whether the constraints are being met.|
- Capture currents and voltages from simulations and pass that information forward into the layout environment, to incrementally design the circuit and layout to meet specifications with layout effects
- Management capabilities enable circuit designers to set electrical constraints and allow layout designers to observe in real time if constraints are being met
For additional insights, read this blog post on Virtuoso Layout Suite for Electrically Aware Design.
- Cadence PCell Designer Datasheet
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- Virtuoso Analog Design Environment XL Datasheet
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- Analog/MS Flow with EAD, Device Checker, and PVS PERC Features
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