Resource Library
Press Releases (35)
- TriEye、ケイデンスのSpectre X Simulatorを用いて次世代CMOSベースSWIRイメージセンサの市場投入期間を短縮
- グローバルファウンドリーズ、ケイデンスとの協業により22FDXプラットフォーム向けMixed-Signal OpenAccess PDKを提供し、高度なミックスドシグナル設計およびmmWave設計を実現
- ケイデンスのデジタル設計およびカスタム設計フローが TSMCのN3プロセステクノロジーで認証を取得
- Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications
- Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation
- Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology
- Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation
- Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies
- ケイデンス、高精度を保ったまま１０倍高速なシミュレーションを提供する 大規模並列処理回路シミュレータSpectre X Simulatorを発表
- Cadence Introduces the Spectre X Simulator, a Massively Parallel Circuit Simulator Delivering Up to 10X Faster Simulation with the Same Golden Accuracy
- Cadence Delivers Advanced Packaging Reference Flow for Samsung Foundry Customers
- Cadence Custom/AMS Flow Certified on Samsung 7LPP Process Technology
- Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
- Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation
- ケイデンス、自動車機能安全規格ISO 26262認証機関TÜV SÜDより 業界初めて包括的な「TCL1適格」認定を取得
- ケイデンス、TSMCと協業、7nm FinFET Plus設計の技術革新を加速
- ケイデンスツールおよびフローがTSMCの12FFCプロセス向けに認証を取得
- Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process
- Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation
- ケイデンスのカスタム/アナログ、デジタルおよびサインオフツール、Samsungの28FDSプロセス技術で認証取得
- ケイデンスのデジタル、サインオフ、およびカスタム/アナログツール、Samsungの7LPPおよび8LPPプロセス技術で利用可能に
- Cadence Custom/Analog, Digital and Signoff Tools Achieve Certification on Samsung 28FDS Process Technology
- ケイデンス、Virtuoso Advanced-Node Platformを7nmプロセス向けに拡張
- ケイデンス、TSMCと協業、新しい12FFCプロセステクノロジーを使用して技術革新を推進
- ケイデンス、TSMC 7nmプロセステクノロジー向けに認証を取得
- インテル・カスタム・ファウンドリー、10nmトライゲートプロセス向けにケイデンスのインプリメンテーションおよびサインオフ・ツールを認証
- Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production
- Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
- Kandou Uses Cadence Analog/Mixed-Signal Timing and Power Signoff Tools to Deliver High-Speed SerDes PHY IP Design on 28nm Process
- Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes
- Cadence Digital, Custom/Analog and Signoff Tools Achieve TSMC Certification for 10nm FinFET Process
- Cadence Implementation and Signoff Tools Certified on Intel Custom Foundry 14nm Process
- Cadence Digital and Custom/Analog Tools Achieve TSMC Certification for 10nm FinFET Early Design Starts
- Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry
- Cadence Announces Virtuoso Liberate AMS, Industry's First Dynamic Simulation Characterization Solution for Mixed-Signal Designs
Webinar (8)
Video (19)
- How to Efficiently Run Electromagnetic Simulation of Full Circuit Blocks
- Accelerate Data Set Processing to Verify Custom and Mixed-Signal Designs
- Stop Trading Analog Simulation Accuracy for Performance
- Multimedia
- Multimedia
- Multimedia
- Multimedia
- Multimedia
- Verifying Data Converters with SPICE Accuracy in Minutes and Hours
- Cadence Spectre XPS FastSPICE Simulator for 10X Faster Throughput
- Faster Mixed-Signal Simulation Ensures Chip Performance
- Spectre XPS Demonstration
- Verifying PLLs with SPICE Accuracy in Minutes and Hours
- CDNLive SV 2014: PMC Improves Visibility and Performance with Spectre APS
- Transistor-Level Reliability Analysis for Advanced Node
- Addressing MCU Mixed-Signal Design Challenges for SoCs and IoT
Datasheet (7)
White Paper (4)
- Revolution by Evolution: Getting to the Next Technology Breakthrough in Analog Simulation
- Analog Reliability Analysis for Mission-Critical Applications White Paper
- Improving Test Coverage and Eliminating Test Ecapes Using Analog Defect Analysis White Paper
- A Faster, More Accurate Approach for System-Level Performance Verification of a Wireless RFIC Design White Paper
