設計の相互依存性が回路性能に与える効果
未来づくりに携わる者にとって、スマートライフを実現する電子システムの創造には、半導体、チップのパッケージ、システム・インターコネクト、ハードウエアとソフトウェアのインテグレーション、システム検証をはじめ、複数のレベルにおいて先進の設計技術が必要となります。個別に対応するような過去の設計手法では、今日設計者が直面している、増大する複雑度、低消費電力への要求、市場投入期間の短縮といった課題に対応できません。成功を収める為には、システム・デザイン・イネーブルメント（SDE）のための包括的環境を構成できる、設計自動化、知財、チップ製造、バリューチェーンを形成するその他の部分のエコシステムのリーダーとの協業が必要です。ケイデンスは、カスタム/アナログ/RFソリューションを、SDE戦略のキーコンポーネントと位置付けています。
カスタムIC設計の重要度の低い部分を選択的に自動化することで、エンジニアは精度を要する重要な部分の設計に専念できるようになります。ケイデンスの回路設計ソリューションでは、Virtuoso® Environment、Spectre® Simulation Solutions、Liberate™ CharacterizationおよびLiberate™ Validation Solutionsとともに電気的特性を考慮したレイアウトアシストツールElectrically aware Design（EAD）とアドバンスノード用フローが提供され、設計コンセプトを迅速かつ正確に入力できるため、設計の意図が自然に回路図の中に現れるよう制御されます。この高度な、寄生を考慮した環境を使用して、多くのアナログ、RF、ミックスシグナル設計の相互依存を抽出して可視化し、回路性能への効果を測定することができます。
Virtuoso Custom IC, Analog, and RF Design
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Video (86)
- Virtuoso Design Platform for Next-Generation Custom IC and System Design
- Toshiba Electronic Device Solutions Overcomes Complexities of Advanced-Node Designs
- Meeting the Challenges of Chip Design Using the Virtuoso Suite
- Advanced Characterization with Cadence Liberate Trio Characterization Suite
- Lumerical and Cadence Partner to Address the State of Photonics
- Virtuoso RF Solution Electromagnetic Analysis
- Virtuoso RF Solution Edit-in-Concert™ Technology
- Faster Circuit Simulation Trends for Analog Circuit Design
- Balancing Accuracy, Performance, and Capacity for Large Analog Designs
- Solving Analog Simulation Challenges in Complex Designs
- GlobalFoundries Expert Insights: Aging Analysis for IoT and Automotive Applications
- STMicroelectronics 20nm Constraint Driven Modgen Flow
- Looking for Efficiency While Leveraging the MathWorks and Cadence Alliance
- Smart EM Simulation Automates Work for RFIC and RF Module Designs
- 次世代のカスタムIC／システム設計向けNew Virtuoso System Design Platform
- New Virtuoso Design Platform for Next-Generation Custom IC and System Design
- NI AXIEM 3D Planar EM Analysis in the Virtuoso Environment
- Overview of the Characterization Interface in Liberate Trio Characterization Suite
- Achieve greater throughput and productivity with Liberate Trio Characterization Suite
- Library Characterization in the Cloud
- Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications
- How to Meet the Quality, High Reliability, and Safety Requirements for Analog and Mixed-Signal ICs in Mission-Critical Applications
- Easily Adopt Electro-thermal Simulation for Your High-Reliability Analog Designs
- Improvements in Modeling Device Aging Analysis: Extending Product Lifetime
- Analog Defect Simulation and Analysis for Complex Systems
- Automotive System Trends and the Integration of Analog Electronic Dependability
- Fast & Efficient Memory Verification and Characterization for Advanced On Chip Variation
- Cadence Legato Memory Solution Verification Overview
- Increase Your Productivity with Cadence Legato Memory Solution
- Legato Memory Solution Characterization Overview
- Virtuoso ADE Explorer, Assembler, and Verifier- hear what people are saying about training
- STMicroelectronics – New flow for Analog Top Level Design
- LG Electronics – New Methodology for Full-Chip RFIC Transceiver Co-Verification
- Introducing New Integration with MathWorks
- Extending the Power of MathWorks MATLAB Inside the Virtuoso ADE Suite
- Combined MathWorks and Cadence Design Flow for Analog/Mixed-Signal IC Development
- Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution
- Ultra-Low Voltage SRAM: Addressing the Characterization Challenge
- PhoeniX Software: Developing First-Time-Right Photonic ICs
- Omni Design: Increased Speed and Accuracy with Spectre XPS
- STMicroelectronics - Improving Productivity with Virtuoso SPD
- austriamicrosystems - Cadence Unified Custom/Analog Flow Success Video
- ams Reduces IC Development Effort by Collaborating with Cadence on Layout Productivity
- Closing Gaps in Mixed-Signal Power Implementation Using a Consistent Power Intent
- Analog/MS Flow with EAD, Device Checker, and PVS PERC Features
- Global Unichip: 20nm Testchip Tapeout with Cadence and TSMC
- STMicroelectronics - Virtuoso Custom/Analog Expert Insights
- Characterizing 22FDX Library at GLOBALFOUNDRIES
- Cadence Pattern Matching and DFM Signoff
- Silicon Labs Leverages Cadence Mixed-Signal Solution for Mixed Signal Simulation, Implementation and Signoff
- Verifying Data Converters with SPICE Accuracy in Minutes and Hours
- Developing ASICs for High-End ground and space apps at Saphyrion
- Cadence Spectre XPS FastSPICE Simulator for 10X Faster Throughput
- Verification Made Easy: Learn How to Avoid Mistakes with Virtuoso ADE Verifier
- Celebrating 25 Years of Virtuoso Innovation
- Easily Explore and Analyze Your Design with Virtuoso ADE Product Suite
- The New Sound of Analog Design: Simplify Design Verification with Virtuoso ADE Product Suite
- Faster Timing Characterization of Analog Macros
- Fairchild Semiconductor Eases Floorplanning Challenges of Mixed-Signal Design with Virtuoso Platform
- New Capabilities for Accelerating High-Speed Routing
- Virtuoso Electrically Aware Design
- Offering Leading Edge Total Solutions - GLOBALFOUNDRIES Design Ready 14nm Eco System
- Virtuoso IPVS for Advanced Node Design
- Advanced Node Multi-Patterning Technologies within Virtuoso Environment
- Producing Analog/Mixed-Signal IP Requires a Best-in-Class Design Flow
- Custom Layout Methodologies with Virtuoso Advanced Node
- Cadence In-Design DFM-LDE Adoption in ST SmartPower PDK
- Using VSR for Chip Routing on ST smARTpower Technologies
- TowerJazz AMS Reference Flow
- Accurate and Faster SoC Signoff with Simulation-Based AMS Characterization
- Place-and-Route in Under a Day for Allegro Microsystems
- How Electrically Aware Design Reduces Iterations
- Faster Mixed-Signal Simulation Ensures Chip Performance
- Liberate MX Product Demonstration
- Analog Devices Raises Productivity with ModGen Tools
- Get Real-Time Electrical Feedback with Cadence Virtuoso Layout Suite for Electrically Aware Design
- Spectre XPS Demonstration
- Freescale Accelerates Layout Via Constraint-Driven Design Flow
- Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM
- Verifying PLLs with SPICE Accuracy in Minutes and Hours
- Addressing MCU Mixed-Signal Design Challenges for SoCs and IoT
- STMicroelectronics Automates Full Custom Analog Layout Flow Using Constraints
- CDNLive SV 2014: PMC Improves Visibility and Performance with Spectre APS
- Transistor-Level Reliability Analysis for Advanced Node
- Verifying the RTL in an Analog Circuit
- PMC Gains Faster Analog IP Verification with Virtuoso Platform
Datasheet (36)
- Cadence PCell Designer Datasheet
- Spectre Simulation Platform Datasheet
- Spectre Extensive Partitioning Simulator (XPS) Datasheet
- Spectre Accelerated Parallel Simulator (APS) Datasheet
- Spectre X Simulator Datasheet
- Liberate Characterization Portfolio Datasheet
- Liberate Trio Characterization Suite Datasheet
- Legato Reliability Solution Cadence
- Quantus Extraction Solution
- Legato Memory Solution
- Virtuoso ADE Verifier Datasheet
- Virtuoso Layout Suite GXL Datasheet
- Virtuoso ADE Assembler Datasheet
- Virtuoso ADE Explorer Datasheet
- Virtuoso Variation Option Datasheet
- Spectre RF Option Datasheet
- Virtuoso Layout Suite L Datasheet
- Allegro Package Designer Plus SiP Layout Option
- Virtuoso Analog Design Environment Family
- Virtuoso Schematic Editor L and XL Datasheet
- Virtuoso Analog Design Environment GXL Datasheet
- Virtuoso Chip Assembly Router Datasheet
- Cadence Physical Verification System Datasheet
- Virtuoso Variation-Aware Implementation Option Datasheet
- Spectre AMS Designer Datasheet
- Virtuoso Layout Suite for Electrically Aware Design Datasheet
- Virtuoso Mixed-Signal Behavioral Modeling Technology Datasheet
- Virtuoso Visualization and Analysis Datasheet
- Virtuoso Analog Design Environment XL Datasheet
- Virtuoso Digital Implementation Datasheet
- Virtuoso DFM Datasheet
- Virtuoso Analog Design Environment L Datasheet
- Virtuoso Custom Design Platform XL Datasheet
- Cadence SiP RF Design Datasheet
- Cadence Space-based Router Datasheet
Customers Success (10)
- Altair and Cadence Success Story
- Moving to UVM-MS to Meet Coverage Goals Case Study
- Cadence and Texas Instruments Success Story
- Cadence and Melexis Success Story
- Cadence and Rohde & Schwarz Success Story
- Cadence and Fuji Electric Success Story
- Cadence and Teradyne Success Story
- Cadence and Realtek Success Story
- Cadence and Multigig Success Story
- Cadence and Spansion Success Story
Press Releases (84)
- Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications
- Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation
- ケイデンスのカスタム/AMSフロー、Samsungの5LPEプロセス技術向けに認証取得
- Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology
- Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation
- Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies
- ケイデンス、高精度を保ったまま１０倍高速なシミュレーションを提供する 大規模並列処理回路シミュレータSpectre X Simulatorを発表
- Cadence Introduces the Spectre X Simulator, a Massively Parallel Circuit Simulator Delivering Up to 10X Faster Simulation with the Same Golden Accuracy
- Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology
- Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design
- グローバルファウンドリーズ、プライマリEDAツールベンダーとしてケイデンスを採用
- Cadence Selected as Primary EDA Tool Vendor by GLOBALFOUNDRIES
- Cadence Delivers Advanced Packaging Reference Flow for Samsung Foundry Customers
- Cadence Custom/AMS Flow Certified on Samsung 7LPP Process Technology
- Cadence Launches Liberate Trio Characterization Suite Employing Machine Learning and Cloud Optimizations
- National Instrumentsとケイデンス、次世代の半導体および RF開発の効率化に向けた協業を発表
- Cadence Design Systems and NI Announce Collaboration to Simplify Next-Generation Semiconductor and RF Development
- ケイデンス、業界初のアナログIC用信頼性考慮設計ソリューションを発表
- Cadence Debuts Industry’s First Analog IC Design-for-Reliability Solution
- ケイデンス、TSMCと協業、5nmおよび7nm+で開発されるモバイル、HPC設計の技術革新を加速
- Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation
- Cadence Supports New TSMC WoW Advanced Packaging Technology
- ケイデンス、システム設計向け機能、5nmを含む先端ノード対応およびシミュレーションドリブンレイアウトにより、Virtuoso Platformを拡張
- Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout
- ケイデンス、自動車機能安全規格ISO 26262認証機関TÜV SÜDより 業界初めて包括的な「TCL1適格」認定を取得
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
- ケイデンスのデジタルフルフローおよびサインオフツール、カスタム/アナログツールがIntel 22FFLプロセステクノロジーで認証を取得、利用可能に
- Cadence Full-Flow Digital and Signoff Tools and Custom/Analog Tools Certified and Enabled for Intel 22FFL Process Technology
- ケイデンス、TSMCと協業、7nm FinFET Plus設計の技術革新を加速
- ケイデンスツールおよびフローがTSMCの12FFCプロセス向けに認証を取得
- Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process
- Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation
- ケイデンス、業界初のメモリー設計・検証向け統合ソリューション、Legato Memory Solutionを発表
- Cadence Announces Legato Memory Solution, Industry’s First Integrated Memory Design and Verification Solution
- ケイデンスのカスタム/アナログ、フルフローデジタルおよびサインオフツールGLOBALFOUNDRIESの7LPプロセスノードで利用可能に
- Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
- ケイデンスのVirtuoso System Design Platform、 IC、パッケージ、ボード間のシームレスな設計フローを提供
- New Cadence Virtuoso System Design Platform Provides Seamless Design Flow Between IC, Package and Board
- ケイデンスのカスタム/アナログ、デジタルおよびサインオフツール、Samsungの28FDSプロセス技術で認証取得
- ケイデンスのデジタル、サインオフ、およびカスタム/アナログツール、Samsungの7LPPおよび8LPPプロセス技術で利用可能に
- Cadence Custom/Analog, Digital and Signoff Tools Achieve Certification on Samsung 28FDS Process Technology
- Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung’s 7LPP and 8LPP Process Technologies
- MathWorksとケイデンス、データマイニングおよび解析を加速する新しい統合環境を発表
- Cadence and MathWorks Announce New Integration to Accelerate Data Mining and Analytics
- ケイデンス、Virtuoso Advanced-Node Platformを7nmプロセス向けに拡張
- ケイデンス、TSMCと協業、新しい12FFCプロセステクノロジーを使用して技術革新を推進
- ケイデンス、TSMC 7nmプロセステクノロジー向けに認証を取得
- Virtuoso Analog Design Environment (ADE)がElectronic Products Magazine社のProduct of the Year賞を受賞！
- Cadence and MathWorks Provide System-Level Simulation Solutions for Mixed-Signal IoT and Automotive Applications
- ケイデンスとTSMC、モバイルおよびHPCプラットフォーム向けに7nm FinFET設計を強化
- Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms
- インテル・カスタム・ファウンドリー、10nmトライゲートプロセス向けにケイデンスのインプリメンテーションおよびサインオフ・ツールを認証
- ケイデンス、ARMとの協業を拡充し、設計工程全体をカバーする業界初のHosted Design SolutionによりカスタムSoC及びIoTシステム設計を加速
- 日立、ミックスシグナル設計検証向けにケイデンスのAMSモデルベース検証手法およびツール群を採用
- STマイクロエレクトロニクス、SmartPowerテクノロジー向けにケイデンスの次世代Virtuosoプラットフォームを導入
- UMC、ケイデンスのVirtuoso LDE Analyzerを28HPC(U)プロセス向けに認証
- ケイデンス、先進的なアナログ検証テクノロジーを搭載した次世代のVirtuosoプラットフォームを発表
- Cadence Unveils Next-Generation Virtuoso Platform Featuring Advanced Analog Verification Technologies and 10X Performance Improvements Across Platform
- ケイデンスの設計ツールがTSMC 7nm設計及び10nm 製品開発向けに認証を取得
- Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production
- Silicon Labs社、ケイデンスのミックスシグナル向け低消費電力フローを使用して設計期間を大幅に削減
- Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
- Kandou、ケイデンスのアナログ/ミックスシグナル・タイミングおよびパワー・サインオフツールを使用して、28nmプロセスで高速SerDes PHY IPを実現
- Kandou Uses Cadence Analog/Mixed-Signal Timing and Power Signoff Tools to Deliver High-Speed SerDes PHY IP Design on 28nm Process
- ケイデンス、LumericalおよびPhoeniX Softwareとの協力によりVirtuosoプラットフォーム・ベースの電子/フォトニックIC向け設計フローを提供
- Cadence Collaborates with Lumerical and PhoeniX Software to Offer Virtuoso Platform-Based Design Flow for Electronic /Photonic ICs
- Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes
- ケイデンスのデジタル、カスタム/アナログ、サインオフのツールがTSMCの10nm FinFETプロセス向け認証を達成
- Cadence Digital, Custom/Analog and Signoff Tools Achieve TSMC Certification for 10nm FinFET Process
- ケイデンスのインプリメンテーションおよびサインオフ・ツールがインテルのカスタム・ファンドリー14nmプロセスで認証取得
- Cadence Implementation and Signoff Tools Certified on Intel Custom Foundry 14nm Process
- ケイデンスのデジタルおよびカスタム/アナログ・ツール群が10nmFinFET早期設計開始用にTSMCの認証を達成
- Cadence Digital and Custom/Analog Tools Achieve TSMC Certification for 10nm FinFET Early Design Starts
- インテルとケイデンス、インテル・カスタム・ファウンドリーのユーザー向け14nmライブラリーのキャラクタライズ・リファレンス・フローのリリースで協業
- Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry
- 日立、ケイデンスのVirtuoso AMS Designerを採用し、ミックスシグナル・チップの検証時間を短縮
- ケイデンス、業界初のミックスシグナル設計向けダイナミック・シミュレーション・キャラクタライゼーション・ソリューションVirtuoso Liberate AMSを発表
- TSMC、16FF+プロセス向けにケイデンスのデジタルおよびカスタム/アナログツールを認証、両社は10nm FinFETでも協業
- TSMCが、16nm FinFETライブラリーのキャラクタライゼーションにケイデンスのソリューションを採用
- オン・セミコンダクター、電気特性を考慮した設計向けにケイデンスのVirtuoso Layout Suiteを採用
- ケイデンス、Spectre XPSをミックスシグナル設計対応に拡大
- TSMCの16nm FinFETプロセスで、ケイデンスのデジタルおよびカスタム/アナログ・ツールがV1.0のDRM認証を取得
- Cadence Introduces New Mixed-signal and Radio Frequency Capabilities to Address Wireless Design Challenges
- Cadence Announces New OrCAD Technology to Help Shorten PCB Design Cycles
White Paper (15)
- Compressing Datasets Created During Silicon Design White Paper
- Revolution by Evolution: Getting to the Next Technology Breakthrough in Analog Simulation
- Consolidating RF Flow for High-Frequency Product Design
- Analog Reliability Analysis for Mission-Critical Applications White Paper
- Improving Test Coverage and Eliminating Test Ecapes Using Analog Defect Analysis White Paper
- Addressing Process Variation and Reducing Timing Pessimism at 16nm and Below White Paper
- Addressing Memory Characterization Capacity and Throughput Requirements with Dynamic Partitioning White Paper
- Save Time and Minimize Errors by Automating Co-Design and Co-Analysis of Chips, Boards, and Packages
- Massively Parallel Electrically Aware Design White Paper
- Plan-Based Analog Verification Methodology White Paper
- Accelerating Monte Carlo Analysis at Advanced Nodes White Paper
- Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment, Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment White Paper
- A Faster, More Accurate Approach for System-Level Performance Verification of a Wireless RFIC Design White Paper
- Taming the Challenges of 20nm Custom/Analog Design White Paper
- Solutions for Mixed-Signal SoC Verification White Paper
Success Story Video (9)
- Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution
- austriamicrosystems - Cadence Unified Custom/Analog Flow Success Video
- Validating Design Intent and Improving Design Quality at Micron
- Characterizing 22FDX Library at GLOBALFOUNDRIES
- Silicon Labs Leverages Cadence Mixed-Signal Solution for Mixed Signal Simulation, Implementation and Signoff
- Faster Timing Characterization of Analog Macros
- Analog Devices Raises Productivity with ModGen Tools
- Freescale Accelerates Layout Via Constraint-Driven Design Flow
- Transistor-Level Reliability Analysis for Advanced Node
Customers
Electrically aware design can enable us to save several iterations on the design of each block sensitive to parasitic effects. Depending on block complexity, design time savings can range from half a day to several days per block.
Martin Kejhar, Senior Technical Staff Engineer and Scientist, ON Semiconductor
カスタムIC／アナログ／RF設計 Products A-Z
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