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    • デジタル設計/サインオフ
      デジタル設計/サインオフ 概要

      Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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        • 3D-IC設計ソリューション
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        • Low Power設計ソリューション
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    • カスタムIC/アナログ/RF設計
      カスタムIC/アナログ/RF設計概要

      Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

      概要 Related Products A-Z

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      • 回路設計
        • Flows/Tools
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        • Virtuoso Liberate MX Memory Characterization Solution
        • Virtuoso Liberate AMS Mixed-Signal Characterization Solution
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        • Liberate LV Library Validation Solution
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        • Flows/Tools
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        • 5G Systems and Subsystems
    • システム設計/検証
      システム設計/検証 概要

      Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

      Verification Suite Related Products A-Z

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    • IP
      IP 概要

      An open IP platform for you to customize your app-driven SoC design.

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    • ICパッケージ設計/解析
      ICパッケージ設計/解析 概要

      Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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      • SI/PI解析ツール
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      • IC/パッケージ/ボード協調設計・検証
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    • SYSTEM INNOVATION
    • システム解析
      システム解析概要

      Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

      Overview Related Products A-Z

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      PCB 設計/解析概要

      Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • ミックスシグナル設計ソリューション

ミックスシグナル設計ソリューション

包括的でアナログ、デジタル相互運用可能な実証済みのミックスシグナルの実装と検証

  • Mixed-Signal Solutions
  • Mixed-Signal Verification
  • Mixed-Signal Implementation
  • Signoff
  • Mixed-Signal Unified Methodology Guide

Key Benefits

  • アナログとデジタルの境界および階層を超えて設計意図や整合性を保ち、市場投入時間を短縮
  • 生産性および設計効率の向上のために最適化された、合理的なフローを提供
  • 優れた予測性によって設計スループットを向上
  • OpenAccessデータベースがグループ間での設計データの共有を容易にし、連携を強化
  • 製品、テクノロジー、IP、サービス、サポート、広範なエコシステムサポートからなる強固な基盤に基づき拡張性の高いソリューション

ミックスシグナル・アプリケーションは、エレクトロニクスと半導体の業界において最も早い速度で成長を遂げている市場セグメントの一つです。モバイル機器でのデジタルTV視聴から、タブレットでの読書、自動運転技術まで、消費者はより多くの場面でより多くのことができる、ということをエレクトロニクスに期待しています。モバイルコミュニケーション、ネットワーキング、電源管理、自動車、医療、画像処理、安全性とセキュリティなど様々なアプリケーションを成長機会と捉えて、多くのシリコンベンダーが再び高性能のアナログ/ミックスシグナルやRFの設計にビジネスの重点を置こうと試みています。

ケイデンスの統合ミックスシグナル設計ソリューションは、包括的かつ相互運用可能な設計環境を提供し、お客様がファースト・シリコンで一発完動し、市場投入時間短縮の目標を達成できるようにサポートしてきた20年以上の知見に裏付けられた実証済なソリューションです。

ミックスシグナル設計の課題

高度なプロセスノードへの移行とともに、さらなる高集積化を図ることは、特に実装と検証の面において、ミックスシグナル設計に以下のような新たな課題をもたらします。

実装に関する主な課題

  • アナログツールとデジタルツール間のシームレスなデータ/制約の共有
  • SoC(system-on-chip)レベルでのミックスシグナルIPの統合
  • 物理設計にかかる所要時間
  • ミックスシグナル設計のサインオフ解析(タイミング、パワー、ノイズ)
  • 設計変更(ECO)の効率

検証に関する主な課題

  • シミュレーション自体の性能
  • シミュレーションモデルの作成
  • アナログとデジタルの設計を共にサポートする、統合された検証メソドロジ
  • Low Power検証を含む、ロジック接続性の検証
  • 正確な消費電力解析
統合されたミックスシグナル設計メソドロジ

ケイデンスのミックスシグナル設計ソリューションは、実装と検証の課題に対処し、包括的で相互運用可能な実証済みのメソドロジを提供します。設計初期段階における設計プラン作成、フロントエンド設計、機能検証、レイアウト、サインオフ、パッケージングなど、すべての設計工程において、アナログチームとデジタルチームが役割分担を共有できます。

  • 包括的:様々な単体製品とテクノロジーを高度なメソドロジで統合
  • 相互運用可能:アナログチームとデジタルチームが同時進行で作業を進める共同設計環境を提供し、共通のOpenAccessデータベースを介し設計データと設計制約を共有して、全体的な設計効率が向上
  • 実証済み:ミックスシグナルの設計コミュニティのニーズに20年以上対処し、数千件ものテープアウトの成功を通じて実証済みなソリューション
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    • Virtuoso Liberate AMS Mixed-Signal Characterization Solution
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  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications
  • UMCとケイデンス、28HPC+プロセス向け アナログ/ミックスシグナルフローの認証で協業
  • Cadence Custom/AMS Flow Certified on Samsung 7LPP Process Technology
  • Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
  • Kandou Uses Cadence Analog/Mixed-Signal Timing and Power Signoff Tools to Deliver High-Speed SerDes PHY IP Design on 28nm Process
  • Media Alert: Cadence to Host Mixed-Signal Technology Summit

Success Story Video (2)

  • Silicon Labs Leverages Cadence Mixed-Signal Solution for Mixed Signal Simulation, Implementation and Signoff
  • S3 Group uses Cadence Mixed-Signal Solution for First-Time-Right Silicon

Datasheet (1)

  • Virtuoso ADE Verifier Datasheet
Videos

How Real Number Modeling Improves Functional Verification for Mixed-Signal SoCs

Freescale Tracks Thousands of Simulations Before Tapeout for Bug-Free Silicon

Addressing Smart Sensor Design Challenges for SoCs and IoT Webinar (IoT Webinar Series - Part 2)

Silicon Labs Leverages Cadence Mixed-Signal Solution for Mixed Signal Simulation, Implementation and Signoff

Allegro Microsystems Improves Efficiency and Productivity with Incisive vManager Solution

X-Fab - Cadence Mixed-Signal Solution

News ReleasesVIEW ALL
  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications 12/02/2019

  • UMCとケイデンス、28HPC+プロセス向け アナログ/ミックスシグナルフローの認証で協業 08/07/2019

  • Cadence Custom/AMS Flow Certified on Samsung 7LPP Process Technology 10/23/2018

  • Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow 02/23/2016

  • Kandou Uses Cadence Analog/Mixed-Signal Timing and Power Signoff Tools to Deliver High-Speed SerDes PHY IP Design on 28nm Process 01/25/2016

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