5G RF module designs for handsets can exploit the very large bandwidth offered by millimeter wave (mmWave), but must also meet significant challenges in linearity, power, and heat necessary to be successful in the handset market. You face intense pressure on form factor with tight integration of RFICs, baseband, power management, discretes, and multiple-input/multiple-output (MIMO) antenna arrays with advanced packaging. And as more bands are added and repurposed for 5G over the next five years or so, there’s an evolution opportunity to improve the modules further, for performance, power, and area (PPA).
RF Module Designs
To achieve such low-power multi-standard modules in such densely packed form factors at such high frequencies takes a new class of RF design tool. For this, we created the Cadence® Virtuoso® RF Solution for co-design of RFIC, package, and module substrates using a free mix of GaAs, GaN, and Si transceiver technologies, developed with the Cadence AWR Design Environment platform.
For initial 5G rollout utilizing existing 4G infrastructure, i.e., 5G NSA (non-standalone), handset data will be 5G and control will be 4G. Potential harmonic interference between the two standards must be addressed through careful filter and power amplifier (PA) design. 5G PA design needs integrated envelope tracking, average power tracking, and back off to maximize handset battery life and the linearity demanded by dense 5G modulation schemes. To address this, the Spectre® X Simulator provides fast simulation speeds and golden accuracy with up to 10X performance improvement.
The Cadence Low-Power Solution ensures power minimization for handset 5G module IC design. This comprehensive solution encompasses architecture optimization, power estimation and analysis, functional verification, implementation and signoff, and IP for digital and mixed-signal designs at both the chip and system level.
The new 5G capabilities also require new high-performance, low-power digital blocks such as beamforming engines, channelizers, and signal conditioners. These highly algorithmic blocks are naturally modeled in C++ or SystemC®, which Cadence Stratus™ High-Level Synthesis (HLS) synthesizes to highly efficient low-power RTL for implementation with the Cadence Low-Power Solution. Moreover, with Stratus HLS, these same algorithmic blocks can be retargeted for other 5G applications with different requirements, ranging from ultra-Iow-power IoT sensors to high-performance basestations.
For digital baseband precoding/combining, beam measurement, and tracking in the 5G transceiver design, Cadence provides the Tensilica® ConnX B20 DSP IP, utilizing the latest Tensilica NX architecture for the 10Gbs and above data rates needed for 5G.
The Tensilica IP provides the needed throughput for 5G handset uplink and downlink, covering the functions of the New Radio-Physical Uplink Control Channel (NR-PUCCH), Uplink Shared Channel (NR-PUSCH), Random Access Channel (NR-PRACH), Downlink Control Channel (NR-PDCCH), and Broadcast Channel (NR-PBCH).
Verification of Chips, Packages and Board Designs
To verify the chip, package, or board designs, Cadence offers verification tools and hardware to speed these complex and very important tasks. The Cadence Palladium® Enterprise Emulation Platform is essential for emulating the design before the chip is finalized. Chip designs can be prototyped using the Cadence Protium™ S1 FPGA-Based Prototyping Platform, which enables early software validation and firmware development. The entire Cadence Verification Suite speeds chip verification, and our Sigrity™ signal integrity (SI) and power integrity (PI) integrated solutions enable fast validation of packages and board.