Resource Library
Video (229)
- How We Push Largest 5nm High-Performance Arm Core to 4GHz Frequency
- A Custom RISC-V SoC in GF 12LP Technology Designed with a Personalized Stylus Common UI Flow
- Pushbutton migration from emulation to prototyping based on Protium platform
- Scaling Semiconductor Design Workflows on AWS
- Google’s Story of Moving EDA to Cloud
- Embracing Cloud for Global, High-performance Design Teams
- Samsung 3nm Cadence AMS Design Reference Flow
- Improved Analog Layout Productivity Using ModGen Template-Driven Layout Reuse Methodology in Virtuoso Environment
- Productive Design: Hardware/Software Co-Verification with Virtual Debugging from Simulation to Prototyping
- Timing Characterization for Custom Analog Block
- Functional Safety Flow for ISO 26262 ASIL-C of D Analysis
- Verification Enhances Confidence in Defense Program Success
- Digital Twin Case Study: Applying Emulation-Based Verification of SoC Using Tactical Software
- The Evolution of Sensing, Computing and Architecture Going from ADAS to Automated Driving
- Updating your Automotive SoC from 16FFC to N7
- Ultra low power processor subsytems with customized memories in 22FDX
- RF/Microwave Design in the Era of Connected Cars
- Physical Implementation Methodology of Arm Cortex-A76AE Processor
- A Flexible Lockstep Architecture for ASIL Compliant DSPs and Controllers
- Is Your Design Functionally Safe?
- Simulate Security Attacks on Your Electronics Design Before Fabrication
- Integrating and Simulating Your Design Before Fabrication
- Accelerate Advanced Node Mixed-signal Simulation with AMS-Flexible Flow and Spectre X Simulator
- Hyperscale Computing and Cadence
- Fujitsu Designing the World’s Leading Innovations with Cadence Intelligent System Design
- Mom, I Have a Digital Twin? Now You Tell Me?
- Marvell Gains High Confidence for Silicon Tapeout Using Palladium Emulator to Validate Processor
- Prototyping Billion-Gate Designs with Protium X1 Prototyping System
- Dynamic Software Analysis in Virtual Platforms- Ericsson Expert Insights
- Early Firmware Development on Palladium and Protium, Enables 1st Silicon Success at Toshiba Memory
- Building better aerospace and defense electronics: emulate before you fabricate
- Automotive safety & quality reference flow using Tensilica ConnX B10 DSP
- オートモーティブ電子システムデザインセミナー 「The Evolution of Sensing, Computing, and Architecture Going from ADAS to Automated Driving」
- オートモーティブ電子システムデザインセミナー 「自動運転車のシステム設計における安全・安心への取り組み」
- オートモーティブ電子システムデザインセミナー 「ポスト・コロナ時代の世界の自動車産業」
- オートモーティブ電子システムデザインセミナー 「ADAS・自動運転システム開発のためのバーチャルテストベッド」
- オートモーティブ電子システムデザインセミナー 「世界初のオープンソース自動運転OS「Autoware」の基本概要とハードウェア領域への展望」
- On-Going Challenges to Using Cloud for EDA
- Introduction to the Cadence Palladium Cloud Solution
- Introduction to the Cadence Cloud-Hosted Design Solution for a Complete Design Flow in the Cloud
- Introduction to the Cadence CloudBurst Platform for Ready-to-Use Peak Capacity
- Introduction to the Cadence Cloud Passport Model
- Introduction to the Cadence Cloud Portfolio
- An Introduction to Cloud Computing for Electronic Design
- A Semiconductor Company’s Typical Cloud Concerns
- Virtuoso RF Solution Electromagnetic Analysis
- Better PPA with Innovus Mixed Placer Technology – Gigaplace XL
- Building Aerospace and Defense Electronics Right the First Time
- Cadence Technology and Services Leveraged in the Automotive Development Process
- Accelerate Data Set Processing to Verify Custom and Mixed-Signal Designs
- Simulate 5G Signal Sources for Complete Signoff Verification
- Improve Device Matching with Assisted Component P&R
- How Row-Based Methodology Improves Custom Layout
- Using Row-Based Methodology to Improve Advanced-Node Custom Layout
- Advanced Methodologies to Accelerate Your Custom Layout
- Digital Twinning and the Future of the Aerospace and Defense Industry
- Avoid Density Gradient Effects in 16FF+ Designs with Virtuoso Layout Suite GXL ModGens
- The Cadence Cloud Portfolio
- Aerospace and Defense Challenges in RF/Microwave Design and Integration
- BabbleLabs Transforms Speech for Digital World Using Cadence Technology
- Cloud Computing for Electronic Design (Are We There Yet?)
- New Cadence Products Expand the Verification Suite: Xcelium Parallel Simulator and Protium S1 Platform
- Design Methodologies for Next-Generation Advanced Multi-Chip(let) Packaging
- STMicroelectronics 20nm Constraint Driven Modgen Flow
- Advanced mm-Wave 3D Imaging Radar Solution Powered by Cadence Tensilica Vision DSP
- Automotive In-Cabin Driver Monitoring System Powered by Cadence Tensilica Vision DSP
- Cadence and Autoware—Partnering to Make Autonomous Vehicles for Tomorrow
- Integrating Video, Radar, and Lidar for Autonomous Driving
- Addressing Digital Implementation Challenges with Innovative Machine Learning Techniques
- Cadence Academic Network - Integrating Video, Radar, and Lidar for Autonomous Driving
- Cadence Academic Network - Chips to Study Natural Intelligence and to Build Artificial Intelligence
- Cadence’s Insight into Design Process Helps the US Technology Leadership Council Achieve its Goals
- Cadence and Uhnder—Partnering to Make Fully Autonomous Driving Possible
- System of Systems Verification and Digital Twins for Aerospace Applications
- Intelligent system design of AI and machine learning applications
- The Importance of Semiconductors for the Fast Changing World of Automotive
- Cloud Passport Partner Program for Academia
- Automotive Sensors: Concepts and Trends
- Challenges for Autonomous Driving
- Design Requirements for Autonomous Driving
- Shortening Development Time to Enable Autonomous Driving
- When it Comes to Cloud-Based Design, One Size Does Not Fit All
- Arm and Cadence collaborate on Arm Neoverse N1 platform to advance Cloud-to-Edge infrastructure
- Addressing 5G System Design Challenges
- Toshiba Electronic Device Solutions Overcomes Complexities of Advanced-Node Designs
- Did You Know - Cadence Aerospace and Defense
- Proven Electronic Design Solutions for Mission-critical Systems
- Systems of Systems Verification and Digital Twins for Aerospace Applications
- Standalone AI Processor: Tensilica DNA 100 Processor IP for On-Device AI
- Designing an SoC on the Cloud
- Whiteboard Wednesdays - Passport Partners Program Expands Customer Cloud Deployment Options
- Whiteboard Wednesdays - Tensilica DSPs, Sensors, and Neural Networks
- Dream CHIP Technologies – Automotive ADAS Chip Architecture
- AI-based Pedestrian Detection powered by Cadence Tensilica
- Digital home assistant speech recognition powered by Tensilica HiFi DSP
- New Cadence Tensilica ConnX B20 DSP for automotive radar/lidar and 5G communications
- Advanced mm-Wave 3D Imaging Radar Solution using Tensilica DSP
- Tensilica Hardware Safety Kit ISO 26262
- Significance of Sparsity in Neural Networks
- A Peek Inside Future Automotive Networks
- Whiteboard Wednesdays - Introduction to Functional Safety From an IP Supplier
- The Truth about Designing for Automotive Functional Safety
- An Introduction to Palladium Cloud
- Introducing the Cloud Passport Model
- Cloud-Hosted Design Solution – a Full-Service Cloud Offering
- The 4 Steps Necessary for an Effective Cloud-Based Design Strategy
- CloudBurst – the Fast, Painless, Proven Solution for Hybrid Cloud Environments
- The Cadence Cloud Portfolio of Fast, Painless, Proven Solutions for Cloud-Based Design
- Simplifying Fault Injection Simulations for Functional Safety Verification
- Getting a Jumpstart on 20nm - Part 2
- Cloud Panelist Introductions
- The Palladium Solution and SoC Emulation for 16nm Automotive Devices at NXP
- From TensorFlow to RTL in three months
- Tensilica Neural Network Compiler: Efficiently Deploy Neural Networks
- Automotive Sensor Design Enablement
- Introduction to ADAS with a Real-Life Example
- Faster Routing by Optimizing FPGA Pin Assignments
- Cadence Cloud – The Future of Electronic Design
- Library Characterization in the Cloud
- AI for Image Classification and Object Detection
- Full HD 360° Surround View enabled by Tensilica Vision P6 DSP
- Protium S1 used to prototype a pedestrian detection application.
- AI for People Detection using Tensilica Vision P6 DSP
- Breaking Down ADAS Sensor Fusion Platforms and Sensor Concepts
- Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications
- Ethernet and Automotive Electronics
- How to Meet the Quality, High Reliability, and Safety Requirements for Analog and Mixed-Signal ICs in Mission-Critical Applications
- Easily Adopt Electro-thermal Simulation for Your High-Reliability Analog Designs
- Improvements in Modeling Device Aging Analysis: Extending Product Lifetime
- Analog Defect Simulation and Analysis for Complex Systems
- Automotive System Trends and the Integration of Analog Electronic Dependability
- Cadence Automotive – from Concepts to Solutions
- The Benefits of Running the Xcelium Parallel Logic Simulator on Cavium’s Arm Based ThunderX2
- A Practical Approach to Failure Modes, Effects, and Diagnostic Analysis (FMEDA)
- Understanding ISO 26262 Implications for Automotive Design Teams
- Automotive Memory Technologies and Trends: Technology Implications
- Summary of Keynote by Davide Santo from NXP on Artificial Intelligence in Autonomous Driving
- Hardent: Solution for Next-Generation Automotive Video Systems Enabled with Cadence IP
- Renesas R-Car Audio Channel Processing using Cadence Tensilica DSP
- Low Power Embedded CNN with Tensilica High-Performance Vision DSP
- Combined MathWorks and Cadence Design Flow for Analog/Mixed-Signal IC Development
- Active Safety Features
- Automotive Functional Safety and the ISO 26262 Standard
- Industry Trends and Requirements for Autonomous Driving
- Radar Signal Processing for Automotive Applications
- Radar Signal Processing Optimized for the Tensilica Fusion G3 DSP
- Modular VIP Architecture
- Memory Trends to Fit Your Application
- Tensilica Vision P6 DSP Enhanced for CNN
- Where Ethernet is Used in Automotive Electronics
- Implementation of Higher Speed PCIe Gen4 IP
- Automotive IP Subsystems
- Big Automotive Trends and Challenges - Lars Reger, NXP Semiconductors
- lars reger nxp role of semiconductor industry in automotive innovation 1080p
- Enhancing Design Productivity at STMicroelectronics with Virtuoso Custom/Analog Flow
- Renesas: Balancing Performance, Low-Power and Functional Safety in ADAS Applications
- Improving Quality and Time-to-Market for TSMC 16nm FinFET Process Using the Cadence Certified Tools and Flow
- How to Design a TSMC 20nm Chip with a Completely Validated Cadence Solution
- Low-Power Mixed-Signal Verification of Freescale Kinetis Products
- 2.2 GHz Performance on 28nm ARM Dual-Core Cortex-A9 Processor
- Closing Gaps in Mixed-Signal Power Implementation Using a Consistent Power Intent
- Developing 4G Wireless Designs with Cadence CPF-Driven Low-Power Solution
- Global Unichip: 20nm Testchip Tapeout with Cadence and TSMC
- How Electronics are Driving the Coolest Features in Today's Cars
- Cadence Implementation, Signoff and DFM Readiness for Samsung FinFET Nodes
- Accurate Low Power verification on a Complex Low Power Design using CLP
- Freeescale Semiconductor - Cadence Low-Power Solution for Kinetis SoC
- Evolution of Electronics in Automotive Industry
- Lars Reger, NXP, Future car- from connectivity to autonomous driving
- Silicon Labs Leverages Cadence Mixed-Signal Solution for Mixed Signal Simulation, Implementation and Signoff
- S3 Group uses Cadence Mixed-Signal Solution for First-Time-Right Silicon
- Emulating Nvidia GPUs
- Cadence virtual hardware in-the-loop environment for ECU design
- Faster Timing Characterization of Analog Macros
- Verify Smarter with Industry's First Datacenter-Class Emulation System
- Cadence DAC 2015 Clio Soft
- Physical Design Flow Challenges at 28nm on Multi-Million Gate Blocks
- Samsung Foundry 14LPP: The Continual Thrust in FinFET Leadership
- Embedded World: Enabling Automotive System Design with Allegro Sigrity Tools
- Offering Leading Edge Total Solutions - GLOBALFOUNDRIES Design Ready 14nm Eco System
- Virtuoso IPVS for Advanced Node Design
- Advanced Node Multi-Patterning Technologies within Virtuoso Environment
- Custom Layout Methodologies with Virtuoso Advanced Node
- TowerJazz AMS Reference Flow
- Physical Design Analytics and DFM Enablement for sub-14nm Technology Nodes
- X-FAB Revamps Low-Power Design Flow with CPF
- Lowering Leakage Power in ARM Cortex-A17 Processor-based SoCs at GLOBALFOUNDRIES
- Faster HW/SW Debug, Embedded Software Development and System Validation
- Xilinx - Industry Leading Solutions for FPGA-based Prototyping
- Freescale Tracks Thousands of Simulations Before Tapeout for Bug-Free Silicon
- Rapid Adoption of Advanced Cadence Design flows Using X-FAB's AMS Reference Kit
- TSMC Europe discusses the importance of 16nm FinFET technology
- IBM and Cadence Collaborate to Solve Advanced Node Design Challenges
- Accelerating design-in of Xilinx FPGAs while optimizing PCB layout for cost and performance
- Accelerating design-in of Altera FPGAs while optimizing PCB layout for cost and performance
- Tackling 16nm Challenges for Arm Cortex-A72 Processor
- Automotive Ethernet Audio Demo: An Overview
- FPGA board design: Introduction to Cadence FPGA System Planner
- Hitachi: Faster Bring Up with Protium Platform
- Arm AMBA Protocol Overview
- Virtuoso Mixed-Signal "SmartPower" Implementation Flow
- Virtuoso Technology for Advanced Process Nodes
- Is SystemVerilog the Future of Analog Behavioral Modeling
- Cadence and GLOBALFOUNDRIES 20nm Reference Flow
- Get real-time electrical feedback on 16FF designs with Virtuoso Layout Suite for Electrically Aware Design
- STMicroelectronics Automates Full Custom Analog Layout Flow Using Constraints
- STMicro Shortens Turnaround Time with Cadence's Mixed-Signal Solutions
- Building Energy Efficient SoCs with big.LITTLE Technology
- TowerJazz Substrate Noise Enablement
- Arm Cortex®-M0 and Cortex-M0+: Tiny, Easy, and Energy-Efficient Processors for Mixed-Signal Applications
- Silicon Signoff and Verification - 16nm FinFET Challenges and Features
- Texas Instruments - Highly Scalable Multicore ARM A15 Verification with Specman/e
- GLOBALFOUNDRIES - Collaboration Keys to Building Complex PDKs
- Addressing MCU Mixed-Signal Design Challenges for SoCs and IoT
- Low-Power Summit ARM Sathya Subramanian
- Efficient Design Verification and Yield Estimation
- Introducing Low-power Verification RAK
- Is SystemVerilog the Future of Analog Behavioral Modeling
- PMC - Power Estimation – An Evolving Science
- Overcoming Patterning-Induced Place-and-Route Challenges at 10nm
- Enabling Cadence Signoff Technologies for 14nm FinFET at Samsung
- How Nvidia is Speeding Up Timing Closure of Advanced-Node Application Processors
- The Best of Both Worlds – Combining Virtual and FPGA-based Prototypes
- Getting a Jumpstart on 20nm - Part 1
- Silicon Labs - Power Mode Verification in Mixed-Signal Chips
- Cadence and IBM - Custom 20nm Solution Webinar
- Design Challenges in Developing Sub-Volt IP Designs for IoT Applications
- Digital 20nm RTL-to-GDSII Methodology
White Paper (31)
- SLAM and DSP Implementation
- 5G Communications with AWR Software
- Load-Pull Analysis for Optimizing PA Performance
- Predicting Critical Metrics for Wireless RF Links
- 5G Primer for MIMO/Phased Array Antennas
- Radar Systems Primer
- System Simulation for RF Link Budget Analysis
- 5G NR Primer for Amplifier and Filter Design
- Design and Physical Realization of Phased Array Antennas for MIMO/Beam Steering Applications
- Cadence Cloud—The Future of Electronic Design Automation White Paper
- A Complete System-Level Security Verification Methodology White Paper
- Automotive Functional Safety Using LBIST and Other Detection Methods
- Accelerating SoC Time to Market with Cloud-Based Verification White Paper
- Improving Test Coverage and Eliminating Test Ecapes Using Analog Defect Analysis White Paper
- DO-254 Explained White Paper
- Accelerating DO-254 Approval with Cadence Tools White Paper
- Meeting the Challenges of the National Defense Strategy
- Functional Safety Methodologies for Automotive Applications White Paper
- A Program Manager’s Guide to Successful Integrated Circuit Verification
- Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment, Addressing the Challenges of Photonic IC Design Via an Integrated Electronic/Photonic Design Automation Environment White Paper
- Plan-Based Analog Verification Methodology White Paper
- A Better Tool for Functional Verification of Low-Power Designs with IEEE 1801 UPF White Paper
- Meeting Functional Safety Requirements Efficiently Via Electronic Design Tools and Techniques White Paper
- Pushing the Performance Boundaries of ARM Cortex-M Processors for Future Embedded Design White Paper
- Techniques to Accelerate Power and Timing Signoff of Advanced-Node SoCs White Paper
- Solutions for Mixed-Signal SoC Verification Using Real Number Models White Paper
- Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components White Paper
- Building Energy-Efficient ICs from the Ground Up White Paper
- Solutions for Mixed-Signal SoC Verification White Paper
- 20nm Design - How this Advanced Technology Node Will Transform SoCs and EDA White Paper
Webinar (17)
- Accelerate Data Set Processing to Verify Custom and Mixed-Signal Designs
- Simulate 5G Signal Sources for Complete Signoff Verification
- Improve Device Matching with Assisted Component P&R
- How Row-Based Methodology Improves Custom Layout
- Using Row-Based Methodology to Improve Advanced-Node Custom Layout
- Advanced Methodologies to Accelerate Your Custom Layout
- Digital Twinning and the Future of the Aerospace and Defense Industry
- Avoid Density Gradient Effects in 16FF+ Designs with Virtuoso Layout Suite GXL ModGens
- Aerospace and Defense Challenges in RF/Microwave Design and Integration
- Cloud Computing for Electronic Design (Are We There Yet?)
- Design Methodologies for Next-Generation Advanced Multi-Chip(let) Packaging
- Combined MathWorks and Cadence Design Flow for Analog/Mixed-Signal IC Development
- Get More Performance and Lower Energy for Automotive Using Tensilica DSPs
- Addressing Smart Sensor Design Challenges for SoCs and IoT Webinar (IoT Webinar Series - Part 2)
- Addressing Smart Sensor Design Challenges for SoCs and IoT (Part 1)
- Arm Cortex®-M0 and Cortex-M0+: Tiny, Easy, and Energy-Efficient Processors for Mixed-Signal Applications
- Understanding the What If to Avoid the What Now
Datasheet (13)
- Radar Systems with AWR Software
- 5G Systems with AWR Software
- Module Design with AWR Software Datasheet
- AWR Software Product Portfolio Datasheet
- Protium S1 FPGA-Based Prototyping Platform
- Legato Reliability Solution Cadence
- Perspec System Verifier Datasheet
- Protium S1 Single-FPGA Board Datasheet
- vManager Metric-Driven Signoff Platform Datasheet
- Virtuoso ADE Verifier Datasheet
- Palladium Z1 Enterprise Emulation Platform Datasheet
- Protium FPGA-Based Prototyping Platform Datasheet
- Allegro FPGA System Planner Datasheet
Press Releases (136)
- ケイデンス、2020年度TSMC OIP Partner of the Yearアワードを4部門で受賞
- ケイデンスのカスタム/AMSフロー、Samsung Foundryの 早期設計開始3nm先端プロセス技術向けに認証を取得
- グローバルファウンドリーズ、ケイデンスとの協業により22FDXプラットフォーム向けMixed-Signal OpenAccess PDKを提供し、高度なミックスドシグナル設計およびmmWave設計を実現
- ケイデンスのデジタル設計およびカスタム設計フローが TSMCのN3プロセステクノロジーで認証を取得
- ケイデンス、TSMCおよびMicrosoftと協業、 クラウド活用により半導体デザインのタイミングサインオフにかかる時間を短縮
- ケイデンスのデジタル設計およびカスタム/アナログ設計EDAフローが TSMCのN6およびN5プロセステクノロジで認証を取得
- ケイデンス、Arm Cortex-A78およびCortex-X1 CPU搭載モバイル機器開発向けに デジタル設計フルフローおよびVerification Suiteを最適化
- ケイデンスのデジタル設計フルフロー、マシンラーニングを活用し、 QoR改善、設計スループット最大3倍高速化の実現に向け最適化
- Dover Microsystems and Cadence Partner to Deliver Secure Processing with Silicon-Layer Security for Mission-Critical Applications
- Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications
- Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation
- ケイデンス、4部門で2019年度TSMC Partner of the Yearアワードを受賞
- Cadence Presented with Four 2019 TSMC Partner of the Year Awards
- ケイデンスの車載向け設計リファレンスフロー、先端ノードデザイン開発においてSamsung Foundryの認証を取得
- ケイデンス、３次元IC向け先端パッケージング統合フローが Samsung Foundryの7LPPプロセス向けに認証取得
- Cadence Collaborates with Arm and Samsung Foundry on Delivery of 5LPE Flow for Mission-Critical Applications Using Next-Generation “Hercules” CPU
- Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies
- UMCとケイデンス、28HPC+プロセス向け アナログ/ミックスシグナルフローの認証で協業
- Cadence and UMC Collaborate on Certification of Analog/Mixed-Signal Flow for 28HPC+ Process
- NSITEXE Accelerates Delivery of Data Flow Processor IP for Automotive and Industrial Applications Using the Cadence Digital Design Full Flow
- Cadence Digital Full Flow Achieves Certification for Samsung Foundry 5LPE Process Technology
- ケイデンス、新しいCloud Passport Partner Programにより ユーザー管理クラウドの選択肢を拡張
- Cadence Expands Customer-Managed Cloud Options with New Cloud Passport Partner Program
- ケイデンス、Preferred NetworksのChainerモデルを Tensilica Vision DSPで利用可能に
- ケイデンスの設計ソリューション、 TSMC-SoIC™ 先進3Dパッケージング技術への対応を発表
- ケイデンス、TSMCと協業し、5nm FinFET技術革新を加速、 次世代SoC製品の設計が可能に
- Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design
- ケイデンス、ハイブリッドクラウド環境に向けた新しいCloudBurstプラットフォーム によりクラウドベース製品におけるリーダーシップを拡大
- Cadence Extends Cloud Leadership with New CloudBurst Platform for Hybrid Cloud Environments
- ケイデンス、ノースロップ・グラマン社とチップ設計に関して協業
- Arm、ケイデンス、Xilinx、 次世代のCloud-to-Edgeインフラストラクチャーに向けにTSMC 7nmプロセス上で 開発された業界初のArm Neoverse System Development Platformを発表
- Arm, Cadence and Xilinx Introduce First Arm Neoverse System Development Platform for Next-Generation Cloud-to-Edge Infrastructure, Implemented on TSMC 7nm Process Technology
- Cadence Tensilica Product Development Process and Software Products Certified for ISO 26262 ASIL D Compliance for Automotive Applications
- Cadence Tools and IP Optimized for New Arm Neoverse N1 Platform to Advance the Cloud-to-Edge Infrastructure Market
- Media Alert: Cadence to Showcase Photonics Applications at Photonics Summit and Workshop with Lumerical
- Cadence Custom/AMS Flow Certified on Samsung 7LPP Process Technology
- Cadence Verification Suite Enabled on Arm-Based HPC Datacenters
- Cadence Accelerates Arm-Based Server Development by Automating Arm Pre-Silicon Bare Metal Compliance Testing
- ケイデンス、4部門でTSMC Partner of the Yearアワードを受賞
- Cadence Recognized with Four 2018 TSMC Partner of the Year Awards
- ケイデンス、Cloudポートフォリオを拡張し、 TSMC OIP Virtual Design Environmentを提供
- ケイデンス、TSMC InFO_MS先進パッケージング技術に対応開始
- Cadence Expands its Cloud Portfolio with Delivery of TSMC OIP Virtual Design Environment
- ケイデンス、モバイル、HPC設計の開発を促進するTSMCの5nmおよび7nm+ FinFETプロセステクノロジーでEDA認証を取得
- Cadence Delivers Support for TSMC InFO_MS Advanced Packaging Technologies
- Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
- ケイデンスのCloud-Hosted Design Solutionが Amazon Web Services Industrial Software Competencyステータスを獲得
- Cadence Achieves Amazon Web Services Industrial Software Competency Status for Its Cloud-Hosted Design Solution
- Cadence Full-Flow Digital Tool Suite Achieves GLOBALFOUNDRIES 22FDX® Certification
- ケイデンス、DARPA ERIの機械学習プロジェクトに採択、電子設計のイノベーションを加速
- Cadence Sigrity 2018をリリース、 3D設計および3D解析の統合によりPCBの設計サイクルを加速
- ローム、機能安全検証ツールを採用、ISO 26262 ASIL D認証を取得
- Cadence Automotive Solution for Safety Verification Used by ROHM to Achieve ISO 26262 ASIL D Certification
- Cadence Full-Flow Digital and Signoff Tools Certified on Samsung Foundry’s 7LPP Process Technology
- Cadence Delivers the First Broad Cloud Portfolio for the Development of Electronic Systems and Semiconductors
- Cadence Collaborates with Amazon Web Services to Deliver Electronic Systems and Semiconductor Design for the Cloud
- Cadence and Microsoft Collaborate to Facilitate Semiconductor and System Design on the Microsoft Azure Cloud Platform
- Cadence Collaborates with Google Cloud to Enable Cloud-Based Development of Electronic Systems and Semiconductors
- Cadence Launches Liberate Trio Characterization Suite Employing Machine Learning and Cloud Optimizations
- Cadence Full-Flow Digital and Signoff Tools and Verification Suite Provide Optimal Results for 7nm Arm Cortex-A76 CPU Designs
- Cadence Debuts Industry’s First Analog IC Design-for-Reliability Solution
- Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation
- ケイデンス、テンシリカ新製品Vision Q6 DSP IPを発表、コンピュータ・ビジョンおよびAI性能を向上
- Cadence Boosts Vision and AI Performance with New Tensilica Vision Q6 DSP IP
- Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout
- ケイデンスとArm、低消費電力かつ高性能なArmサーバー上で起動する 初のSoC検証ソリューションを提供
- ケイデンス、自動車機能安全規格ISO 26262認証機関TÜV SÜDより 業界初めて包括的な「TCL1適格」認定を取得
- Cadence Announces Digital and Signoff Flow Support for Body-Bias Interpolation for GLOBALFOUNDRIES 22FDX™ Process Technology
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
- Cadence Delivers Design and Analysis Flow Enhancements for TSMC InFO and CoWoS® 3D Packaging Technologies
- Xilinx、Arm、ケイデンス、TSMC、7nmプロセステクノロジーで世界初のCCIXシリコンテストチップを発表
- Cadence Full-Flow Digital and Signoff and Verification Suite Optimized to Support Arm Cortex-A75 and Cortex-A55 CPUs and Arm Mali-G72 GPU
- ケイデンスのFunctional Safety Verification SolutionがロームのISO 26262準拠の車載IC開発フローに採用
- Cadence Functional Safety Verification Solution Adopted for ISO 26262-Compliant Automotive IC Development Flow at ROHM
- 名古屋大学とケイデンスが協業、テンシリカのプロセッサーおよびDSPにAUTOSAR準拠のTOPPERS Automotive Kernelを移植
- Nagoya University and Cadence Collaborate to Port AUTOSAR-Compliant TOPPERS Automotive Kernel to Tensilica Processors and DSPs
- ケイデンス、ARM DesignStart顧客向けにオンラインでのツールアクセスを拡充し、SoC設計の開発を加速
- Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
- Cadence Expands Online Tool Access for ARM DesignStart Customers to Accelerate SoC Design Delivery
- Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung’s 7LPP and 8LPP Process Technologies
- ケイデンス、Virtuoso Advanced-Node Platformを7nmプロセス向けに拡張
- Cadence Unveils Expanded Virtuoso Advanced-Node Platform for 7nm Processes
- ケイデンス、TSMCと協業、新しい12FFCプロセステクノロジーを使用して技術革新を推進
- ケイデンス、自動車機能安全規格ISO 26262に対応する業界初の包括的なTCL1ドキュメントを提供
- Cadence Delivers Industry’s First Comprehensive TCL1 Documentation to Support Automotive ISO 26262 Standard
- ケイデンス、ARMの新しいプロセッサーCortex-M23、Cortex-M33の早期実装およびサインオフを実現
- Cadence Enables Accelerated Implementation and Signoff of New ARM Cortex-M23 and Cortex-M33 Processors
- Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms
- Cadence Delivers Integrated System Design Solution for TSMC InFO Packaging Technology
- ケイデンス、ARM Cortex-R52 CPUの早期実装およびサインオフを実現するRapid Adoption Kitを提供
- Cadence Delivers Rapid Adoption Kit for Fast Implementation and Signoff of New ARM Cortex-R52 CPU
- Cadence Debuts PSpice Web Portal and Ecosystem to Help Designers Address System Level Mixed-Signal Wireless and IoT Challenges
- ケイデンス、ARMとの協業を拡充し、設計工程全体をカバーする業界初のHosted Design SolutionによりカスタムSoC及びIoTシステム設計を加速
- Cadence Expands Collaboration with ARM to Accelerate Custom SoC and IoT System Designs with Industry’s First End-to-End Hosted Design Solution
- ケイデンス、ARMのCoretex-A73 CPUおよびMali-G71 GPUコア向け10nmリファレンスフローのRAK（Rapid Adoption Kits）を提供
- Cadence Delivers Rapid Adoption Kits Based on a 10nm Reference Flow for New ARM Cortex-A73 CPU and ARM Mali-G71 GPU
- Uurmi Fog Removal Software Now Available on Cadence Tensilica Vision DSPs
- Cypress Adopts Cadence Digital Implementation and Circuit Simulation Tools for 40nm Automotive Designs
- Tezzaron Cuts Design Time in Half with Cadence Full-Flow Digital RTL-to-Signoff Solution
- Cadence Announces New Tensilica Vision P6 DSP Targeting Embedded Neural Network Applications
- Cadence Digital and Signoff Tools Certified on Samsung Foundry's 14LPP Process
- Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production
- 先進運転支援システムのための交通標識認識システムの開発期間をプロトタイピング・プラットフォームにより70%削減
- Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
- Building the Car of the Future Today-Cadence Showcases Automotive Solutions at embedded world 2016
- Kandou Uses Cadence Analog/Mixed-Signal Timing and Power Signoff Tools to Deliver High-Speed SerDes PHY IP Design on 28nm Process
- ケイデンス、LumericalおよびPhoeniX Softwareとの協力によりVirtuosoプラットフォーム・ベースの電子/フォトニックIC向け設計フローを提供
- Cadence Collaborates with Lumerical and PhoeniX Software to Offer Virtuoso Platform-Based Design Flow for Electronic /Photonic ICs
- ケイデンス、10nmプロセスに向けたVirtuoso Advanced-Node Platformを発表
- Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes
- Cadence Receives Customers' Choice Award for Automotive IP Paper Presented at TSMC OIP Ecosystem Forum
- ケイデンス、ARM AMBA 5 AHB5向けの検証IPを発表
- Cadence and ARM Deliver an IP Reference System for Internet of Things Applications
- Cadence Announces Verification IP for ARM AMBA 5 AHB5
- Cadence Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 22FDX Platform Reference Flow
- Media Alert: Cadence to Host Mixed-Signal Technology Summit
- Cadence and ARM Announce Strategic IP Interoperability Agreement
- Cadence Announces Fourth Generation Tensilica HiFi DSP Architecture
- GLOBALFOUNDRIESとケイデンス、ARM Cortex-A17プロセッサーを搭載した28nm-SLPプロセス初のSoCイネーブルメント/ソリューションを実現
- ケイデンス、 ISO 26262準拠の準備労力を最大50%削減する、自動車向け機能安全検証ソリューションを発表
- ケイデンス、車載アプリケーション向けにMüller-BBMのActive Noise ControlおよびActive Sound DesignをテンシリカHiFiオーディオ・ボイスDSPに移植し最適化
- Cadence Introduces Automotive Functional Safety Verification Solution, Reducing ISO 26262 Compliance Preparation Effort by up to 50 Percent
- Müller-BBM Active Noise Control and Sound Design Now Optimized on Cadence Tensilica HiFi Audio/Voice Processors for Automotive Applications
- ARMとケイデンス、TSMCの超低消費電力テクノロジー・プラットフォームを利用するIoTおよびウェアラブル機器アプリケーション向けの協力を強化
- ARMがケイデンスのPalladium XPプラットフォームとARM Fast Modelsの併用により、Mali GPUの開発でOS立ち上げ時間を50倍に高速化
- ARMとケイデンスは、複数年の技術アクセス協定締結によりSoC設計の協力を拡大
- SPL Vitalizer In-Car Audio Software Now Available on Cadence Tensilica HiFi Audio/Voice DSP Family
- Cadence and QNX Announce New Tensilica HiFi Audio/Voice DSP Application for In-Car Active Noise Control
- ARMとケイデンス、64ビットのプロセッサー設計での協業を拡大
- CSR、ARMベースの車載用インフォテイメント・システム開発向けにケイデンスのPalladium XPプラットフォームを選択
- CSR Selects Cadence Palladium XP Platform for Development of ARM-based Automotive Infotainment Systems
- ARM、先端ノードのファウンデーションIP開発向けに、ケイデンスのライブラリ・キャラクタライズ・ソリューションを採用
- ヤマハ、Cadence Low-Power Solution を使用してモバイル向け最新チップのリーク電流を50%削減
- ケイデンス、ARMベースのシステム検証ソリューションを拡張、モバイル、ネットワーク、およびサーバ・アプリケーション向けに製品の市場投入期間を短縮
- Cadence Expands ARM-based System Verification Solution, Reducing Time-to-Market for Mobile, Networking and Server Applications
- Cadence Announces Sensor Platforms as New Tensilica HiFi Audio Partner for Sensor Fusion and Context Awareness Applications
Presentation (21)
- Embracing Cloud for Global, High-performance Design Teams
- New Virtuoso Design Platform
- Speed Up Your Mixed-Signal Verification with Spectre X Simulator
- Quantus Extraction Solution for Accurate and Fast Silicon Signoff and Verification
- Co-Design of Chip and Package with Virtuoso System Design Platform Presentation
- Creating Liberty Models for Custom and Mixed-Signal Blocks Presentation
- Best Practices for Verifying Mixed-Signal Systems Presentation
- Analyzing Mismatch and Predicting Yield in Virtuoso ADE Assembler Presentation
- Measuring the Impact of Aging in Spectre and ADE Presentation
- Using Spectre RF Analyses for Non-RF Circuits Presentation
- Getting The Most Out Of Spectre APS Presentation
- Building Analog Self-Checking Presentation
- Accounting for Calibration/Trimming in ADE Presentation
- Model-Based Verification of Mixed-Signal SoCs
- Mixed-Signal Design Challenged: From Transistors to Systems
- AnaViP:vaUVM-MS Component to Drive and Monitor Analog Signals
- DSP-Assisted RF, analog, and Mixed-Signal Design
- Connecting MATLab and Simulinlk to Cadence Virtuosos AMS Designer
- Making the Design Simpler and More Efficient
- Cadence and GLOBALFOUNDRIES 20nm Reference Flow
- Bluetooth Smart and Low-Power Innovation
Customer Presentation (15)
- A Custom RISC-V SoC in GF 12LP Technology Designed with a Personalized Stylus Common UI Flow
- Pushbutton migration from emulation to prototyping based on Protium platform
- Scaling Semiconductor Design Workflows on AWS
- Google’s Story of Moving EDA to Cloud
- Samsung 3nm Cadence AMS Design Reference Flow
- Improved Analog Layout Productivity Using ModGen Template-Driven Layout Reuse Methodology in Virtuoso Environment
- Productive Design: Hardware/Software Co-Verification with Virtual Debugging from Simulation to Prototyping
- Timing Characterization for Custom Analog Block
- Functional Safety Flow for ISO 26262 ASIL-C of D Analysis
- Verification Enhances Confidence in Defense Program Success
- Digital Twin Case Study: Applying Emulation-Based Verification of SoC Using Tactical Software
- The Evolution of Sensing, Computing and Architecture Going from ADAS to Automated Driving
- Updating your Automotive SoC from 16FFC to N7
- Physical Implementation Methodology of Arm Cortex-A76AE Processor
- Is Your Design Functionally Safe?
Article (10)
- Making AUTONOMOUS VEHICLES affordable
- Developing Military Electronic Systems Calls for Holistic Strategy
- Emulate Before You Fabricate: A Mantra for Defense Electronics
- Preventing Expensive Electronic Hardware Mistakes
- Consumer Electronics Break Augustine's Laws
- Realizing the Potential of AI on the Edge
- Virtual is Real With Electronic Systems Prototyping
- Understanding 5G for the DoD
Customers
Due to the Palladium Z1 platform's capacity to handle our billion gate-class designs and its highly sophisticated debug and advanced multiuser capabilities, all in a small form factor, we will be able to design and deliver our next generation GPU and Tegra designs with high quality and on schedule.
Narenda Konda, Director of Engineering, NVIDIA
Processors for automotive and industrial markets are driving higher levels of integration and complexity. This requires larger design partitions to deliver the efficiencies and time to market demanded by our customers.
Anthony Hill, Director of Processor Technology, Texas Instruments
Electrically aware design can enable us to save several iterations on the design of each block sensitive to parasitic effects. Depending on block complexity, design time savings can range from half a day to several days per block.
Martin Kejhar, Senior Technical Staff Engineer and Scientist, ON Semiconductor