Computational Software: Foundation for an Optimal Digital Design and Signoff Full Flow

Integration between synthesis and placement to improve design optimization is so important that we gave this technology a name, which we call iSpatial. Interconnect layers in a modern process all have very different capacitance and resistance profiles, so deciding how to use them must be done early and involves techniques such as layer assignment, useful clock skew and via pillars. The iSpatial technology allows a seamless transition from the Cadence Genus Synthesis Solution to the Cadence Innovus Implementation System using a common integrated physical optimization, common user interfaces (UIs) and a common database exchange.

When a design requires a week of runtime, it is very important. Saving 10% saves about a day. A reduction like this can result from all sorts of reasons: Better scalability in the cloud (being able to use 48 machines instead of 32), better algorithms (a faster placer) or better integration (for example, between the placement engine and the timing engine).

Over the last several years, Cadence has created a digital full flow with common integrated engines, driving technology leadership. Of course, development is never over, but this gives us the platform to move into the future. Advanced nodes—5nm, 3nm, and beyond—are still very important to our most advanced customers.

Another computational software trend is to use machine learning (ML) to steer the underlying algorithms and thus improve results. One of the limiting factors in any advanced SoC design is having enough designers available. In some ways, running EDA tools has something in common with running a nuclear power plant: A lot of it is very repetitive, but you absolutely need the best engineers. ML allows computation, especially in the cloud, to substitute for routine human interaction, and thus, it can drive a major increase in productivity. In much the same way as a goal for cars is autonomous driving, but we have to get there through incremental steps. The goal for the digital full flow is eventual front-to-back automation, sometimes called, “no human in the loop”. But, as with cars, we have to approach through incremental steps—perhaps we can call that, “fewer humans in the loop”. When an engineer is running a tool, looking at the result, and then tweaking some parameters before running the flow again, there are a lot of opportunities to tweak the parameters automatically, at least some of the time. We can also capture the decisions of the best designers, and thus deliver some of their expertise to less experienced teams. It enables an engineering team to get more done.

There is also plenty of scope for improving predictability. At some level, each tool in the flow has a standard of “goodness” that is tied up in how well it integrates with the next stage. A good placement of the design is one that the global router handles well. A good global route of the design is one that the detail router can handle well, and so on. Almost all the algorithms in EDA are computationally intractable in the sense that getting the exact optimal solution is not possible. Instead, heuristics are used. But this is another area where ML can be used, with heuristics at one level using ML to better predict how things will be downstream.

Better prediction leads to both a better result, and, at least potentially, a faster conclusion due to the reduction in the amount of iteration required. Diagrams of a flow always look much more linear than they really are, since there is so much iteration going on both under the hood of most tools and in the flow with which the tool is repeatedly invoked.

All of this reminds me of a remark by a comedian who said, “it takes a lot of practice to make it look unrehearsed”. In the digital full flow, it takes a lot of computation and iteration to make it look smooth and linear.

The Cadence digital full-flow contains best-in-class engines, together with best-in-class integration to make everything work cleanly together. Adding ML improves productivity even more. You need best-in-class digital computational software to create and sign off best-in-class results.

Let me give you an example of best-in-class results from a GM at one of the top 10 semiconductor companies, who is in charge of CPU and AI design, that highlights his experience using our latest ML capabilities to train a model of their CPU core. The project resulted in both an improved maximum clock frequency and stunning 80% reduction in total negative slack. That’s a bit of a geeky measure that might not mean much. Let me say that it’s a big number. But it’s not just a number—it resulted in a 2X shorter turnaround time for final signoff design closure.

To wrap up, the scale of computational software that is used in the digital and signoff flow is orders of magnitude larger than algorithms in other industries. The fact that people can design systems with billions of transistors is the most obvious evidence of that. The largest planes in the world contain about four million parts. Compared to digital implementation, that is a small number.

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