Global Unichip: 20nm Testchip Tapeout with Cadence and TSMC

Watch this video for insights into Global Unichip's successful tapeout of a 20nm testchip with Cadence and TSMC. Albert Li, marketing director at Global Unichip, talks about the collaborative effort and overcoming advanced node challenges such as double patterning and new design rules.

最終変更: June 1, 2016