Highlights:
- Cadence delivers 7nm digital implementation and signoff RAK for the development of Arm Neoverse N1-based designs
- Cadence Verification Suite and its engines enhance verification throughput for engineers creating Neoverse N1-based designs
- Cadence DDR4 PHY IP, CCIX IP, and PCIe 4.0 PHY IP integrated and with Neoverse N1 SoC, driving key I/O interfaces to peak levels of performance
- Arm Neoverse N1 System Design Platform and board based on Neoverse N1 platform and Cadence IP was implemented and verified using Cadence tools in support of CCIX cache coherency for asymmetrical compute acceleration
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its tools and IP have been optimized to support the new Arm® Neoverse™ N1 platform to accelerate the transformation of a scalable cloud-to-edge infrastructure. To ease adoption, Cadence delivered a 7nm full-flow digital implementation and signoff Rapid Adoption Kit (RAK), collaborated with Arm to ensure the Cadence® Verification Suite and its engines improve designer throughput, and integrated Cadence DDR4 PHY IP, CCIX IP and PCI Express® (PCIe®) 4.0 PHY IP. Additionally, the Neoverse N1 System Design Platform (SDP), based on the Neoverse N1 platform and Cadence IP, was implemented and verified using Cadence tools to support Cache Coherent Interconnect (CCIX) for asymmetrical compute acceleration.
7nm Digital Implementation and Signoff RAK
The RAK for Neoverse N1 includes the Cadence full-flow digital implementation and signoff tools that utilize Arm 7nm POP™ IP libraries. The comprehensive Cadence RTL-to-GDS flow enables customers to accelerate physical implementation and signoff to speed time to market. The RAK also includes comprehensive documentation and scripts outlining how customers can achieve optimal power, performance and area (PPA) goals with new devices. The tools in the flow include the Innovus™ Implementation System, Genus™ Synthesis Solution, Conformal® Equivalence Checking, Conformal Low Power, Tempus™ Timing Signoff Solution and the Quantus™ Extraction Solution.
Cadence Verification Suite
Cadence delivered a full verification and emulation suite to support the Neoverse N1 platform including Xcelium® Parallel Logic Simulation Platform, Palladium® Z1 Enterprise Emulation Platform, JasperGold® Formal Verification Platform, vManager™ Planning and Metrics, Perspec™ System Verifier and the Cadence Verification IP (VIP) portfolio with the Cadence Interconnect Workbench. The powerful combination of the Cadence Verification Suite and its engines improve verification throughput for engineers creating Neoverse N1-based designs.
Cadence IP
Cadence DDR4 PHY IP, CCIX IP and PCIe 4.0 PHY IP have been integrated and proven in silicon with the Neoverse N1 platform, driving key I/O interfaces to peak levels of performance. Arm selected the Cadence IP for the integration due to its strong feature set and maturity with silicon proof-points at 7nm.
Neoverse N1 SDP
Cadence also collaborated with Arm on the delivery of the Neoverse N1 SDP. The N1 SDP is based on the Neoverse N1 platform and Cadence DDR4 PHY IP, CCIX IP and PCIe 4.0 PHY IP that enables asymmetrical compute acceleration via CCIX for application areas like machine learning / artificial intelligence (AI), 5G and analytics. A full Cadence tool flow was used to implement and verify the SDP, and customers can begin software development immediately and shorten overall time to market.
“The Neoverse N1 platform delivers the latest high-performance compute with optimal power consumption to support the diverse compute requirements of the next-generation infrastructure from hyperscale to edge access,” said Drew Henry, senior vice president and general manager, Infrastructure Line of Business, Arm. “Through our continued collaboration with Cadence, customers can enhance their development environments to quickly differentiate themselves with their next-generation Neoverse-based solutions.”
“We worked closely with Arm to optimize our advanced digital implementation and signoff solutions, the Cadence Verification Suite and our IP for the Neoverse N1 platform so our customers can efficiently create innovative 7nm designs,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “As part of this collaboration, Cadence provided tools and IP for the Arm Neoverse N1 SDP, and customers can begin designing Neoverse SDP-based systems immediately.”
Cadence-Arm Seminars
To further facilitate adoption of the Neoverse N1 platform, a series of seminars will be held during Q2 2019, where customers can learn how to implement the new processor using the Cadence tools and IP. Seminars are being planned in the following locations:
- Bangalore, India
- Beijing, China
- Shanghai, China
- Hsinchu, Taiwan
- Petah Tikvah, Israel
To learn more about the Cadence Arm-based solutions that support the Neoverse N1 platform, please visit www.cadence.com/go/armn1. For more information on the full-flow digital implementation and signoff solutions, please visit www.cadence.com/go/disan. For more information on the Cadence Verification Suite, visit www.cadence.com/go/vsan. For more information the Cadence IP solutions, visit www.cadence.com/ipan.
