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Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
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Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
Reference flow available for early customer engagement
DESIGN AUTOMATION CONFERENCE, AUSTIN, Texas, 20 Jun 2017
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its custom/analog and full-flow digital and signoff tools are now enabled for v0.5 of the GLOBALFOUNDRIES 7nm Leading-Performance (7LP) FinFET semiconductor technology. The 7LP process node is expected to deliver 40 percent better performance and twice the area scaling than the previous 14nm FinFET technology.
GF has enabled the Cadence® implementation tools and reference flow for the 7LP platform, providing high-volume customers with the ability to create reliable, advanced-node chips for the high-performance compute (HPC), server/datacenter, premium mobility AP, machine learning and vision processing markets. To learn more about the Cadence full-flow digital and signoff solutions in the flow, visit www.cadence.com/go/gf7lpdands. For information about the Cadence custom/analog solutions in the flow, visit www.cadence.com/go/gf7lpcanda.
Cadence collaborated with GF on the development of the 7LP Process Design Kit (PDK), which is available for early customer designs. The tools in the flow include:
Innovus™ Implementation System: An advanced physical implementation tool, incorporating a massively parallel architecture that helps designers deliver high-quality SoCs in less time with best-in-class PPA
Genus™ Synthesis Solution: An RTL synthesis and physical synthesis engine that improves productivity challenges faced by RTL designers, delivering up to 5X faster synthesis turnaround times
Tempus™ Timing Signoff Solution: A complete timing analysis tool that improves signoff timing closure via massively parallel processing and physically aware timing optimization
Quantus™ QRC Extraction Solution: A parasitic extraction tool that provides faster runtimes for single- and multi-corner extraction and best-in-class accuracy versus foundry golden
Voltus™ IC Power Integrity Solution: A cell-level power integrity solution supports comprehensive electromigration and IR drop (EM/IR) design rules and requirements while providing full-chip SoC power signoff accuracy
Voltus-Fi Custom Power Integrity Solution: A transistor-level power integrity solution supports comprehensive EM/IR design rules and requirements while providing SPICE-level power signoff accuracy for analog, memory and custom digital IP blocks
Physical Verification System: Includes advanced technologies and rule decks to support design rule checks (DRCs), layout versus schematic (LVS), advanced metal fill, yield-scoring, voltage-dependent checks and in-design signoff
Manufacturability and Variability Solutions (MVS): Delivers design-for-manufacturability (DFM) and variability analysis and optimization, including in-design detection and automated fixing
Spectre® Classic Simulator, Spectre Accelerated Parallel Simulator (APS) and Spectre eXtensive Partitioning Simulator (XPS): These products deliver fast and accurate circuit simulation of complex analog, radio frequency (RF) and mixed-signal circuits with full support for advanced-node device models and parasitics
Virtuoso® Analog Design Environment (ADE) Product Suite: Enables engineers to fully explore, analyze and verify designs, ensuring that variation is addressed and design quality is fully optimized within compressed design cycles
Virtuoso Layout Suite: Supports custom/analog, digital, and mixed-signal designs at the device, cell, block, and chip levels, offering accelerated performance and productivity
Virtuoso Schematic Editor: Provides numerous capabilities to facilitate fast and easy design entry, including design assistants that speed common tasks by as much as 5X
Virtuoso Liberate™ Characterization Solution: Anultra-fast standard cell, I/O, memory and complex multi-bit-cell library characterization solution that generates electrical cell views for timing, power and signal integrity, including advanced current source models (CCS and ECSM)
“High-volume semiconductor companies working to migrate to advanced-node designs can begin to use our 7LP process now,” said Alain Mutricy, senior vice president of product management at GF. “We’ve collaborated with Cadence to ensure that its tools are supported at advanced nodes, enabling customers to create high-performance products for servers and datacenters, 5G connectivity, vision processing, and automotive.”
“Cadence custom/analog, digital and signoff customers can engage with us now to start realizing the benefits of the GF 7LP process node and achieve power, performance and area goals,” said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and System & Verification Group at Cadence. “Our work with GF demonstrates our joint commitment to enabling customers to create innovative SoCs that meet advanced technical requirements and aggressive time-to-market deadlines.”
About Cadence
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.
