Home
  • 製品
    • DESIGN EXCELLENCE
    • デジタル設計/サインオフ
      デジタル設計/サインオフ 概要

      Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

      Full-Flow Digital Solution Related Products A-Z

      製品カテゴリー
      • 等価性検証
        • ソリューション/フロー
        • Conformal Equivalence Checker
        • Conformal Smart LEC
      • SoC Implemenation and Floorplanning
        • ソリューション/フロー
        • Innovus Implementation System
        • First Encounter Design Exploration and Prototyping
        • Virtuoso Digital Implementation
      • 機能ECO
        • ソリューション/フロー
        • Conformal ECO Designer
      • Low Power検証
        • ソリューション/フロー
        • Conformal Low Power
      • 高位/論理合成
        • ソリューション/フロー
        • Stratus High-Level Synthesis
        • Genus Synthesis Solution
        • Virtuoso Digital Implementation
      • パワー解析
        • ソリューション/フロー
        • Joules RTL Power Solution
      • SDC and CDC Signoff
        • ソリューション/フロー
        • Conformal Litmus
        • Conformal Constraint Designer
      • シリコン・サインオフ/検証
        • ソリューション/フロー
        • Pegasus Verification System
        • Quantus Extraction Solution
        • Tempus Timing Signoff Solution
        • Assura Physical Verification
        • Physical Verification System
        • CMP Predictor
        • MaskCompose Reticle and Wafer Synthesis
        • QuickView Signoff Data Analysis
        • LDE Electrical Analyzer
        • Process Proximity
        • Pattern Analysis
        • Litho Physical Analyzer
        • Voltus IC Power Integrity Solution
        • Voltus-Fi Custom Power Integrity Solution
      • Library Characterization
        • ソリューション/フロー
        • Liberate Trio Characterization Suite
        • Liberate MX Memory Characterization
        • Liberate AMS Mixed-Signal Characterization
        • Liberate LV Library Validation Solution
        • Liberate Characterization Solution
        • Liberate Variety Statistical Characterization
      • テスト
        • ソリューション/フロー
        • Modus DFT Software Solution
      • ソリューション/フロー
        • ソリューション/フロー
        • 3D-IC設計ソリューション
        • Advanced Node設計ソリューション
        • Armベース設計向け検証ソリューション
        • Library Characterization Flow
        • Low Power設計ソリューション
        • ミックスシグナル設計ソリューション
    • カスタムIC/アナログ/RF設計
      カスタムIC/アナログ/RF設計概要

      Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

      概要 Related Products A-Z

      製品カテゴリー
      • 回路設計
        • Flows/Tools
        • What's New in Virtuoso
        • Virtuoso Schematic Editor
        • Virtuoso ADE Product Suite
      • 回路シミュレーション
        • Flows/Tools
        • Spectre Simulation Platform
        • Spectre X Simulator
        • Spectre eXtensive Partitioning Simulator
        • Spectre RF Option
        • Spectre AMS Designer
      • ライブラリ・キャラクタライゼーション
        • Flows/Tools
        • Liberate Trio Characterization Suite
        • Virtuoso Liberate MX Memory Characterization Solution
        • Virtuoso Liberate AMS Mixed-Signal Characterization Solution
        • Liberate Variety Statistical Characterization
        • Liberate Characterization Solution
        • Liberate LV Library Validation Solution
      • レイアウト設計
        • Flows/Tools
        • What's New in Virtuoso
        • Virtuoso Layout Suite
      • レイアウト検証
        • Flows/Tools
        • Virtuoso DFM
        • Physical Verification System
        • Virtuoso Integrated Physical Verification System
      • ソリューション/フロー
        • Flows/Tools
        • Electrically Aware Designソリューション
        • Advanced Node設計ソリューション
        • Virtuoso RF Solution
        • Virtuoso System Design Platform
        • Legato Memory Solution
        • Legato Reliability Solution
        • 5G Systems and Subsystems
    • システム設計/検証
      システム設計/検証 概要

      Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

      Verification Suite Related Products A-Z

      製品カテゴリー
      • デバッグ解析
        • Flows/Tools
        • Indago Debug Platform
        • Indago Debug Analyzer App
        • Indago Embedded Software Debug App
        • Indago Protocol Debug App
        • SimVision Debug
      • ハードウェア・エミュレーション
        • Flows/Tools
        • Palladium Z1 Enterprise Emulation System
        • Palladium Dynamic Power Analysis
        • Palladium Hybrid
        • SpeedBridge Adapters
        • VirtualBridge Adapters
        • Emulation Development Kit
        • Virtual JTAG Debug Interface
        • Accelerated VIP
        • QuickCycles Services
      • フォーマル/スタティック検証
        • Flows/Tools
        • JasperGold Formal Verification Platform (Apps)
        • Assertion-Based Verification IP
      • FPGAプロトタイピング
        • Flows/Tools
        • Protium S1 Desktop Prototyping Platform
        • Protium X1 Enterprise Prototyping Platform
        • SpeedBridge Adapters
      • 検証プランニング/マネージメント
        • Flows/Tools
        • vManager Metric-Driven Signoff Platform
      • シミュレーション/テストベンチ生成・検証
        • Flows/Tools
        • Xcelium Parallel Simulator
        • Incisive Enterprise Simulator
        • Incisive Functional Safety Simulator
        • Incisive Specman Elite
      • ソフトウェア・ドリブン検証
        • Flows/Tools
        • Perspec System Verifier
        • Indago Embedded Software Debug App
        • Virtual System Platform
      • 検証IP
        • Flows/Tools
        • Accelerated Verification IP
        • Assertion-Based VIP
        • Verification IP (VIP) Catalog
      • ソリューション/フロー
        • Flows/Tools
        • Armベース設計向け検証ソリューション
        • オートモーティブ機能安全ソリューション
        • メトリック・ドリブン検証ソリューション
        • ミックスシグナル検証ソリューション
        • Low Power機能検証ソリューション
    • IP
      IP 概要

      An open IP platform for you to customize your app-driven SoC design.

      More

      製品カテゴリー
      • Interface IP
        • IP
        • PCI Express IP
        • CCIX IP
        • USB IP
        • SerDes IP
        • Ethernet IP
        • MIPI IP
        • HD Display IP
      • Denali Memory IP
        • IP
        • NAND Flash IP
        • DDR IP
        • HBM2 IP
        • SD / SDIO / eMMC IP
        • Octal and Quad SPI Flash Controller and PHY IP
      • テンシリカ DSP IP (USサイト)
        • IP
        • HiFi DSPs for Audio, Voice, and Speech
        • ConnX DSPs for Radar, Lidar, and Communications
        • Vision DSPs for Imaging, Vision, and AI
        • Fusion DSPs for IoT
        • DNA Processor Family for On-Device AI
        • Tensilica Customizable Processors
        • Tensilica Reference Configuration
      • Analog IP
        • IP
        • Analog IP
      • System / Peripherals IP
        • IP
        • 8051 Microprocessor IP
        • System Bus Peripherals
        • Audio Controllers
      • 検証IP (USサイト)
        • IP
        • Accelerated VIP
        • Assertion-Based VIP
        • Memory Models
        • Simulation VIP
        • Productivity Tools
        • Interconnect Solution
    • ICパッケージ設計/解析
      ICパッケージ設計/解析 概要

      Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

      概要 Related Products A-Z

      製品カテゴリー
      • ICパッケージ設計
        • Flows/Tools
        • Allegro Package Designer
        • SiP Digital Architect
      • ICパッケージ向けSI/PI解析ソリューション
        • Flows/Tools
        • Allegro Sigrity SI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity Package Assessment and Extraction Option
        • Allegro Sigrity PI Base
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI解析ツール
        • Flows/Tools
        • Sigrity PowerSI
        • Sigrity PowerDC
        • Sigrity OptimizePI
        • Sigrity System Explorer
        • Sigrity Speed2000
        • Sigrity SystemSI
        • Sigrity Broadband SPICE
        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity XtractIM
        • Sigrity XcitePI Extraction
      • IC/パッケージ/ボード協調設計・検証
        • Flows/Tools
        • OrbitIO Interconnect Designer
        • IO-SSO Analysis Suite
      • ソリューション/フロー
        • Flows/Tools
        • Substrate設計ソリューション
        • IC/パッケージ/ボード協調設計ソリューション
        • InFO パッケージ設計ソリューション
        • Sigrityテクノロジー最新情報
        • Virtuosoとの統合設計環境
        • PDN(power delivery network)設計
    • SYSTEM INNOVATION
    • システム解析
      システム解析概要

      Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

      Overview Related Products A-Z

      製品カテゴリー
      • Electromagnetic Solutions
        • Tools
        • Clarity 3D Solver
        • Sigrity XcitePI Extraction
        • Sigrity XtractIM
        • Sigrity PoweSI
      • Thermal Solutions
        • Tools
        • Celsius Thermal Solver
      • Flows
    • FPGAプロトタイピング
    • PCB設計/解析
      PCB 設計/解析概要

      Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

      概要 Related Products A-Z Service Bureaus

      製品カテゴリー
      • 回路設計
        • Flows/Tools
        • Allegro Design Entry Capture/Capture CIS
        • Allegro Design Publisher
        • Allegro Design Authoring
        • Allegro FPGA System Planner
      • プリント基板レイアウト
        • Flows/Tools
        • Allegro PCB Designer
        • OrCAD PCB Designer(外部サイト)
      • ライブラリ/設計データ管理
        • Flows/Tools
        • Electrical CAD-Mechanical CAD Library Creator
        • Allegro EDM Solution
        • Allegro PCB Librarian
        • Allegro Pulse
      • アナログ/ミックスシグナル・シミュレーション
        • Flows/Tools
        • Allegro PSpice Simulator
        • OrCAD Pspice Designer(外部サイト)
      • PCB設計向けSI/PI解析ソリューション
        • Flows/Tools
        • Allegro Sigrity Serial Link Analysis Option
        • Allegro Sigrity SI Base
        • Allegro Sigrity PI Base
        • Allegro Sigrity Power-Aware SI Option
        • Allegro Sigrity PI Signoff and Optimization Option
      • SI/PI解析ツール
        • Flows/Tools
        • Sigrity PowerSI
        • Sigrity PowerDC
        • Sigrity OptimizePI
        • Sigrity System Explorer
        • Sigrity SystemSI
        • Sigrity Speed2000
        • Sigrity Broadband SPICE
        • Sigrity Transistor-to-Behavioral Model Conversion (T2B)
        • Sigrity PowerSI 3D EM Extraction Option
      • Allegro最新情報
        • Flows/Tools
        • Board Layout
        • Schematic Capture
        • Data Management
      • Sigrity最新情報
        • Flows/Tools
        • Sigrity 2018 Release
        • Sigrity Tech Tips
      • ソリューション/フロー
        • Flows/Tools
        • Multi-Board PCB System Design
        • システム製品開発ソリューション
        • 電気系CAD/機械系CAD 協調設計
        • Allegro Right First-Time Design
        • IO同時スイッチング解析ソリューション
        • 3D System Design Solutions
        • PDN設計ソリューション
        • LPDDR4 ソリューション
        • パワー考慮シグナル・インテグリティ解析ソリューション
        • インターフェース設計向けソリューション
        • Sigrityシリアル信号解析ソリューション
    • PERVASIVE INTELLIGENCE
    • テンシリカ DSP IP (USサイト)
    • 機械学習
    • spacer
    • クラウド対応
    • 全製品(アルファベット順)
  • ソリューション
    • INDUSTRIES
    • 5Gシステム/サブシステム
    • 航空宇宙/防衛
    • オートモーティブ
    • TECHNOLOGIES
    • 3D-IC設計
    • Advanced Node
    • Armベース・ソリューション
    • クラウド対応
    • FPGA Development
    • Low Power
    • 機械学習
    • ミックスシグナル
    • フォトニクス
  • サービス
    • サービス 概要

      Helping you meet your broader business goals.

      More

    • デザイン・サービス
    • トレーニング
    • メソドロジー・サービス
    • VCADサービス
  • サポート
    • サポート
      Support Overview

      A global customer support infrastructure with around-the-clock help.

      More Cadence Online Support Portal

      • Support Process
        • 24/7 Support - Cadence Online Support

          Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.

          Visit Now

        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

          Visit Now

      • Computing Platform Support
        • 24/7 Support - Cadence Online Support

          Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.

          Visit Now

        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

          Visit Now

      • Customer Support Contacts
        • 24/7 Support - Cadence Online Support

          Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.

          Visit Now

        • Software Downloads

          Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.

          Visit Now

    • spacer
    • トレーニング・コース
    • Custom IC / Analog / RF Design
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Circuit Design and Simulation
        • Featured Courses
        • Analog Design Environment - L
        • SKILL Language Programming Fundamentals
        • Spectre Simulations Using Virtuoso ADE
        • Design Checks and Asserts
        • Virtuoso Schematic Editor
        • Mixed-Signal Simulations Using Spectre AMS Designer
        • Spectre eXtensive Partitioning Simulator for Mixed-Signal Designs
        • Additional Courses
      • Infrastructure & Infrastructure v6
        • Featured Courses
        • Analog Design Environment - L
        • SKILL Development of Parameterized Cells
        • SKILL Language Programming Fundamentals
        • Virtuoso Schematic Editor
      • Layout Design and Verification
        • Featured Courses
        • Quantus QRC Transistor-Level Parasitic Extraction
        • Virtuoso Schematic Editor
        • Quantus QRC Extraction Series
        • Using Virtuoso Constraints Effectively
      • Modeling
        • Featured Courses
        • Analog Modeling with Verilog-A
        • Mixed Signal Simulations Using AMS Designer
        • Mixed-Signal IP and Testbench Reuse
        • Virtuoso ADE Explorer Series
      • Physical Design
        • Featured Courses
        • SKILL Language Programming Fundamentals
        • SKILL Development of Parameterized Cells
        • Virtuoso Layout Suite XL/GXL
        • Virtuoso Layout Suite-L
        • Virtuoso Schematic Editor
        • Virtuoso Schematic Editor (VSE) Interface Virtuoso Layout Suite Flow
        • Spectre Accelerated Parallel Simulator
      • Update
        • Featured Courses
        • Virtuoso Layout Suite XL/GXL
      • Variation Aware Design
        • Featured Courses
        • Analog Design Environment-XL/GXL
        • Spectre Simulations Using Virtuoso ADE
        • High-Performance Simulation Using Spectre Simulators
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

    • Language and Methodology Courses for Chip and SPB Design
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Formal Verification
        • Featured Courses
        • Essential SystemVerilog for UVM
      • SystemVerilog and UVM
        • Featured Courses
        • Verilog Language and Application
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

    • Digital IC Design
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Chip Design
        • Featured Courses
        • Innovus Digital Implementation System
      • Formal Verification
        • Featured Courses
        • Encounter Conformal ECO
      • Logic Design
        • Featured Courses
        • Genus Synthesis Solution
      • Signoff and Analysis
        • Featured Courses
        • Voltus Power-Grid Analysis and Signoff
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

      • Block and Hierarchical Implementation
      • Synthesis
        • Featured Courses
        • Advanced Synthesis with Genus Stylus Common UI
        • Genus Synthesis Solution with Stylus Common UI
        • Low-Power Synthesis Flow with Genus Stylus CommonUI
    • IC Package Design and Analysis
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • IC Packaging
        • Featured Courses
        • Allegro Package Designer
      • Infrastructure
        • Featured Courses
        • Allegro Sigrity SI Foundations
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

    • System Design and Verification
      Training Overview

      Get the most out of your investment in Cadence technologies through a wide range of training offerings.

      Overview All Courses Asia Pacific EMEANorth America

      Tools Categories
      • Formal Verification
        • Featured Courses
        • JasperGold Formal Fundamentals
      • Low Power
        • Featured Courses
        • Incisive Function Coverage
      • Simulation, Testbench and Debug
        • Featured Courses
        • Incisive Function Coverage
        • Indago Debug Analyzer App
        • Incisive Functional Safety Simulator
        • Incisive Simulation Performance Optimization
        • Low-Power Simulation with IEEE Std 1801 UPF
        • Xcelium Fault Simulator
        • Xcelium Integrated Coverage
      • Verilog and VHDL
        • Featured Courses
        • Verilog Language and Application
      • Delivery Methods
        • Instructor-Led Training

          Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.

          Read more

        • Online Training

          Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.

          Read more

  • コミュニティ
    • Blog (USサイト)
      Blogs

      Exchange ideas, news, technical information, and best practices.

      All Blogs

      • Breakfast Bytes
      • Cadence Academic Network
      • Cadence Support
      • Custom IC Design
      • Digital Implementation
      • Functional Verification
      • IC Packaging and SiP Design
      • The India Circuit
      • Insights on Culture
      • Mixed-Signal Design
      • PCB Design
      • RF Design
      • Signal and Power Integrity (PCB/IC Packaging)
      • Silicon Signoff
      • System Design and Verification
      • Tensilica, Design IP and Verification IP
      • Whiteboard Wednesdays
      • All Blog Categories
    • 技術フォーラム(USサイト)
      Technical Forums

      The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.

      All Forums

      • Custom IC Design
      • Custom IC SKILL
      • Digital Implementation
      • Functional Verification
      • Functional Verification Shared Code
      • Hardware/Software Co-Development Verification and Integration
      • IC Packaging and SiP Design
      • High-Level Synthesis
      • Logic Design
      • Mixed-Signal Design
      • PCB Design
      • PCB SKILL
      • PCell Designer
      • RAVEL DRC Programming for IC Packaging and PCS
      • RF Design
      • All User Forums
    • 一般情報(USサイト)
      General Topics Forums

      It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.

      • Announcements
      • Feedback, Suggestions, and Questions
  • 会社案内
    • 会社概要

      Cadence is a leading provider of system design tools, software, IP, and services.

      概要

    • Intelligent System Design
    • カルチャー
    • Environmental Sustainability
    • エグゼクティブ・チーム
    • 取締役会
    • コーポレート・ガバナンス
    • Cadence Academic Network
    • 投資家情報
    • 採用
    • イベント
    • 広報コンテンツ
    • お客様メッセージ
  • ログイン
  • Region
    • 米国本社
    • 中国
    • 韓国
    • 台湾
    • 各国オフィス所在地
  • お問い合わせ
サーチ
メニュー

シェア

  • Home
  •   :  
  • 会社案内
  •   :  
  • 広報コンテンツ
  •   :  
  • Press Releases
  •   :  
  • 2015
  •   :  
  • 10 Mar 2015

Cadence Introduces Innovus Implementation System, Delivering Best-in-Class Results with Up to 10X Reduction in Turnaround Time

SAN JOSE, Calif., 10 Mar 2015

  • Provides typical 10 to 20 percent production-proven advantage in power, performance and area
  • First massively parallel implementation solution in the industry, enabling unprecedented speed and capacity
  • Supports advanced 16/14/10nm FinFET and established process nodes
  • Next-generation platform eases usability and boosts engineering productivity
Cadence Design Systems, Inc. (NASDAQ: CDNS) today unveiled Cadence® Innovus™ Implementation System, its next-generation physical implementation solution that enables system-on-chip (SoC) developers to deliver designs with best-in-class power, performance and area (PPA) while accelerating time to market. Driven by a massively parallel architecture with breakthrough optimization technologies, the Innovus Implementation System provides typically 10 to 20 percent better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10nm FinFET processes and established process nodes.

For more information on the Innovus Implementation System, please visit www.cadence.com/news/innovus.

The Innovus Implementation System was designed with several key capabilities to help physical design engineers achieve best-in-class performance while designing for a set power/area budget or realize maximum power/area savings while optimizing for a set target frequency. The key Innovus capabilities to achieve this include:
  • New GigaPlace solver-based placement technology that is slack-driven and topology-/pin access-/color-aware, enabling optimal pipeline placement, wirelength, utilization and PPA, and providing the best starting point for optimization
  • Advanced timing- and power-driven optimization that is multi-threaded and layer aware, reducing dynamic and leakage power with optimal performance
  • Unique concurrent clock and datapath optimization that includes automated hybrid H-tree generation, enhancing cross-corner variability and driving maximum performance with reduced power
  • Next-generation slack-driven routing with track-aware timing optimization that tackles signal integrity early on and improves post-route correlation
  • Full-flow multi-objective technology enables concurrent electrical and physical optimization to avoid local optima, resulting in the most globally optimal PPA
The Innovus Implementation System also offers multiple capabilities that boost turnaround time for each place-and-route iteration. Its core algorithms have been enhanced with multi-threading throughout the full flow, providing significant speedup on industry-standard hardware with 8 to 16 CPUs. Additionally, the Innovus Implementation System features the industry's first massively distributed parallel solution that enables the implementation of design blocks with 10 million instances or larger. Multi-scenario acceleration throughout the flow improves turnaround time even with an increasing number of multi-mode, multi-corner scenarios.

In addition to providing best-in-class PPA and optimized turnaround time, the Innovus Implementation System offers a common user interface (UI) across synthesis, implementation and signoff tools, and data-model and API integration with the Tempus™ Timing Signoff solution and Quantus™ QRC Extraction solution. Together these solutions enable fast, accurate, 10nm-ready signoff closure that facilitates ease of adoption and an end-to-end customizable flow. Customers can also benefit from robust visualization and reporting that enables enhanced debugging, root-cause analysis and metrics-driven design flow management.

"At ARM, we push the limits of silicon and EDA tool technology to deliver products on tight schedules required for consumer markets," said Noel Hurley, general manager, CPU group, ARM. "We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM® Cortex®-A72 processor. This demonstrated a 5X runtime improvement over previous projects and will deliver more than 2.6GHz performance within our area target. Based on our results, we are confident that the new physical implementation solution can help our mutual customers deliver complex, advanced-node SoCs on time."

"Customers have already started to employ the Innovus Implementation System to help achieve higher performance, lower power and minimized area to deliver designs to the market before the competition can," said Dr. Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence. "The early customers who have deployed the solution on production designs are reporting significantly better PPA and a substantial turnaround time reduction versus competing solutions."

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com


© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks and Innovus, Quantus and Tempus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other trademarks are the property of their respective owners.

Media Contacts

For more information, please contact:

Cadence Newsroom

408.944.7039

newsroom@cadence.com

  • Products
  • システム設計/検証
    デジタル設計/サインオフ
    カスタムIC/アナログ/RF設計
    ICパッケージ設計/解析
    PCB設計/解析
    全製品(アルファベット順)
  • IP
  • テンシリカ・プロセッサ
    インターフェースIP
    デナリ・メモリーIP
    アナログIP
    システムIP/ペリフェラルIP
    検証IP
  • Support
  • オンラインサポート
    トレーニング
    ソフトウェア・ダウンロード
    Resource Library
  • News
  • プレスリリース
    広報コンテンツ
    ブログ
    フォーラム
  • Company
  • 概要
    投資家情報
    Alliances
    エグゼクティブ・チーム
    イベント
    採用情報
    Cadence Academic Network
A Great Place to Do Great Work!

Fifth year on the FORTUNE 100 list

Our Culture
Join the Team
  • Contact Us
  • お問い合せ
    カスタマー・サポート
    プレスリリース
    各国のオフィス
Subscribe to Monthly Newsletter

Email *

Please confirm to enroll for subscription!

Thank you for subscribing. You will get an email to confirm your subscription.

  • Terms of Use
  • Japan Privacy Policy
  • Cadence Privacy Policy
  • US Trademarks
  • © 2019 Cadence Design Systems, Inc. All Rights Reserved.

Connect with Us