CadenceTECHTALK (Japan): 機能検証ソリューション・セミナー Verification Throughput and Smart Bug Hunting with the Cadence Verification Suite

このWebinarシリーズでは、広い設計対象に対応する検証への要求を満たし、設計品質向上と開発工期短縮の双方を達成する手法について解説いたします。

CadenceTECHTALK (Japan): デジタルIC設計ソリューション・セミナー 2020 @HOME

高いレイアウト予見性と最高のPPAを実現する合成ツールのGenus™のご紹介、業界標準となりつつあるデジタル・インプリメンテーション・ツールのInnovus™の新機能紹介、また難易度の高い設計に必須となる統合されたサインオフソリューションをご紹介します。

Webinar: Digital Implementation and Signoff – A Full Flow Overview

Bigger and more complex designs translate to more challenging PPA targets. To meet these challenges, the Cadence integrated digital full-flow offers innovations that work across individual tool boundaries through the integration of core engines and key technologies. Watch this webinar to learn how the Cadence digital full flow and its underlying products can help you beat your PPA goals ahead of schedule.

Webinar: Chip-Level Thermal Analysis Using Celsius Thermal Solver

Transient thermal analysis is a critical factor in understanding thermal behavior, and the impact of dynamic thermal management on the performance of a chip, even more so for applications like automotive, data center, mobile, healthcare, and high-performance computing

CadenceTECHTALK (Japan): AWRオンライン・セミナー 2020 -July

AWR製品の技術的なご紹介、ケイデンスの各種製品と連携したソリューションについてご紹介します。

Webinar Series: Finding Verification Pitfalls Before They Get You

What if you could reduce rework by stamping out the pitfalls much earlier in the design cycle, saving countless hours of design frustration when you are up against your release deadlines? Join our four-part webinar series to learn about advanced verification techniques that can be applied to RF and analog designs, as well as a methodology for tracking your progress to final specification coverage of your analog/mixed-signal designs.

CadenceTECHTALK (Japan): ミックスシグナル・カスタムIC設計セミナー 基本ツール編

ミックスシグナル・カスタムIC設計では業界標準としてご利用いただいているケイデンスのVirtuosoプラットフォームの最新情報をご紹介するWebinarです。​​

Webinar: Full Flow Power Analysis and Optimization

Attend this webinar. We will cover the Cadence solutions for power analysis and optimization starting with early system-level analysis, through RTL-level architecture/microarchitecture, low power implementation, and finally to silicon signoff. Limited to Cadence customers with access to the digital implementation flow.

Jasper User Group 2020 – Call For Presentations Open

Ready to share and discuss the latest design and verification best practices with your peers from around the world?