8-9 June 2021
|Date||EVENT NAME||TECHNOLOGY||Location||Event Type|
|18 Jan 2021 - 28 Feb 2021||
This webinar is intended for Allegro PCB Editor users who wish routing with speed and efficiency using Allegro Interconnect Flow Planner (IFP). The Allegro IFP provides the technology and methodology to capture as well as adhere to a designer’s intent. Through the Allegro IFP’s architecture and global route engine, users can, for the first time, put their experience and design intent into a tool that understands what they want—natively.
|01 Mar 2021 - 04 Mar 2021||
Visit Cadence at DVCon U.S., where we will introduce you to the latest tools, methodologies, and support you need for verifying complex silicon, SoCs, and systems. Join us for a keynote, tutorials, and workshops, and talk to our experts in our virtual booth about the Cadence Verification Suite that delivers the highest verification throughput in the industry
|Palladium, Protium, Xcelium, System Design and Verification, JasperGold, Verification IP||Online||Industry Conference|
|04 Mar 2021||
|05 Mar 2021||
|Clarity, Celsius||Online||Cadence Event|
|11 Mar 2021||
Processor verification has always been a significant challenge. Join Cadence and Axiomise in this webinar and learn how we can change the processor verification status quo and how can we enable a seamless adoption of formal verification for RISC-V processors using the Axiomise RISC-V processor verification app formalISA and Cadence’s JasperGold Formal Verification Platform.
|11 Mar 2021||
Learn how you can use the Voltus IC Power Integrity Solution to run hierarchical analysis using IP modeling technology to create xPGV models of your IP blocks, accurately capturing the demand current and electrical parasitics.
|16 Mar 2021||
See the latest signal integrity, power integrity, and interconnect extraction tools and how you can streamline your DDR5 interface analysis and tackle the challenges of multi-fabric power integrity analysis. See how the latest Sigrity PowerSI, PowerDC, and other Sigrity tools can streamline your PCB and IC Package design cycles.
|17 Mar 2021||
Join Cadence Training and Software Architect Efrat Shneydor for this free, one-hour live technical webinar. We’ll explain Specman macros syntax for e and include numerous code examples. After the webinar, you’ll be able to implement your own macros—to be used in your environment and even to share with the verification community.
|24 Mar 2021||
Distributing circuit and electromagnetic (EM) simulations across multiple processors on a single computer or external remote computer farms can dramatically reduce overall simulation time for resource-intensive MMIC, RFIC, and cross-fabric design problems Hear how Recon-RF’s engineers use the distributed EM analysis option in Cadence RF solutions to accelerate product development and improve high-frequency amplifier performance.
|RF Microwave Design||Online||Cadence Event|
|19 Apr 2021 - 23 Apr 2021||
This year, the Linley Spring Processor Conference will feature live-streamed presentations addressing processors and IP cores for AI applications, embedded, data center, automotive, and server designs. Join us as we introduce our comprehensive portfolio of DSP solutions—ranging from ultra-high-end mobile and multi-camera applications to always-on sensor and IoT applications.
|Tensilica processors||Online||Industry Conference|