We are entering a new era of electronic design automation. Using machine learning technology, we are delivering a first-of-its-kind, scalable and automated digital design flow, from RTL to GDS, that enables any designer to achieve their PPA goals much easier and quicker. Like autonomous driving for chip design! The Cadence Cerebrus Intelligent Chip Explorer uses a unique reinforcement learning algorithm that optimizes multiple steps in the design flow simultaneously, not just one. It can help to overcome growing complexity of designs at 7nm and below, enabling 10x engineering productivity with massive cloud scalability, and producing better PPA.