| 1 | Digital IC Design Flow Overview (part 1) | Digital IC Design Flow Overview (part 2) |
| 2 | Basics of Semiconductors | The Scale of the IC Challenge |
| 3 | Digital IC Functional Design Overview
Hardware Implementation: Data Representation
| HW Imp: Combinatorial Building Blocks
HW Imp: Clocked Building Blocks; Synchronous Design
| Basic Exercises |
| 4 | HW Imp: Arithmetic Building Blocks
HW Imp: Arithmetic Implementation and Optimization
| HW Imp: Finite State Machines
HW Imp: Memory Structures
|
| 5 | Functional Verification Overview
Simple Interactive Debug Techniques with Xcelium
| Verilog 1: Verilog Introduction
Verilog 1: Choosing Datatypes
| 3 verilog Labs |
| 6 | Verilog 2: Operators
Verilog 2: Procedural Statements
| Verilog 3: Blocking and Nonblocking Assignment
Verilog 3: Understanding the Simulation Cycle
| 9 Verilog Labs |
| 7 | Verilog 4: Functions and Tasks
Verilog 4: Directing the Compiler
| Verilog 5: The Synthesis Process
Verilog 5: Coding RTL for Synthesis
| 4 Verilog Labs |
| 8 | Verilog 6: Designing FSMs
Verilog 6: Avoid Simulation Mismatches
| Verilog 7: Verilog Design Example
Verilog 7: Selected System Tasks and Functions
| 6 Verilog Labs |
| 9 | Verilog 8: Generating Test Stimulus
Verilog 8: Developing a Testbench
| Simulation Automation and Scripting | 1 Verilog Lab
1 Tcl Script Lab |
| 10 | Functional Design Challenges part 1: X_propagation,
Clock Domain Crossing, Reset Domain Crossing
| Functional Design Challenges part 2: Clocking gating,
Low Power Concepts; Intro to Low Power Simulation
| Demos |
| 11 | Introduction to a Modern Verification Flow | Introduction to MDV and Planning | |
| 12 | Overview of SystemVerilog (SV) and selected Design enhancements | Selected SV Verification enhancements | 4 SV Labs |
| 13 | Introduction to Coverage | Assertion Based Verification (ABV)
Introduction to SystemVerilog Assertions (SVA)
| 2 XIC Coverage Labs
1 SV Assertion Lab |
| 14 | Overview of UVM | Introduction to Emulation and Rapid Prototyping
Hybrid and Rapid Prototyping
| 1 Simple UVM demo Lab
2 more UVM Labs |
| 15 | Overview of Formal Analysis | Design & Verification flow recap
The Verification Completeness Problem
Summary + links to further tool courses
| Demo Video of Jasper |
