Digital Design and Signoff Academic Curriculum Training

This Digital Design and Signoff Academic Curriculum contains the materials to teach a semester (15-week) course as well as links to Cadence courses with practical hands-on labs using Cadence tools.

The video lectures in the course, presented by Prof. Adam Teman of Bar Ilan University, provide additional context and explanations for the downloadable lecture files.

Educators have the freedom to choose which lectures to teach – use all the modules in the curriculum or only those that are most appropriate to their teaching outcomes. 

The student will explore the complete Digital Design flow, including Verilog HDL Language, synthesis, implementation, STA concepts, and signoff.

This course is comprised of lectures. The labs for this course are contained in Cadence tools courses (Learning Maps), and each tool course has an associated Cadence software to use for the labs. The links to the Cadence courses are included in the downloadable course syllabus.

The following are the lecture modules and the syllabus for a semester curriculum:

You must have knowledge of the following:

• Basic VLSI concepts.
• Basic ASIC Flow
• Basic Knowledge of UNIX/LINUX

• Semiconductor101 Training
• CadenceRTL-to-GDSII Flow Training
• XceliumSimulator
• Verilog Language and Application Training
• Genus Synthesis Solution with Stylus Common UI
• InnovusBlock Implementation with Stylus Common UI
• Tempus Signoff Timing Analysis and Closure with Stylus Common UI
• VoltusPower Grid Analysis and Signoff with Stylus Common UI Training
• Fundamentalsof IEEE 1801 Low-Power Specification Format Training