Analog/Mixed Signal Circuit Modeling Domain Certification Training

After completing this course, you will be able to:

• Determine the importance of the top-down design methodology for accelerating complex system development
• Create, edit, and simulate a variety of analog models written in the Verilog-A language using the Virtuoso^® ADE Explorer and the command-line environment
• Write behavioral models of electrical circuits using the correct Verilog-A language and syntax
• Apply the concepts of behavioral modeling and know when to employ models to your advantage
• Create Verilog, Verilog-A, and Verilog-AMS behavioral models to perform the given functions
• Verify the functionality and performance of the models that you create using the Spectre^® AMS Designer Simulator
• Identify how Real Number Modeling using Verilog-AMS (wreal) enables high-performance digital-centric, mixed-signal verification
• Create Verilog-AMS wreal models
• Use the advanced wreal modeling features
• Identify how wreal connections are resolved in mixed designs
• Apply the wreal modeling techniques for creating models
• Identify how Real-Number Modeling (RNM) using SystemVerilog enables high-performance digital-centric, mixed-signal SoC verification
• Create real-number models with SystemVerilog real variables and nettypes
• Identify SystemVerilog 2012 Extended Nettype Capabilities (built-in, UDT/UDR) and Interconnects
• Examine the Cadence package “EE_pkg” that defines nettype “EEnet" for electrical pin modeling
• Explore advanced SVRNM features and Connect Modules (CM) for AMS interactions
• Identify how SV port connections are resolved in mixed designs using wildcard (.*) notation
• Improve performance with incremental elaboration at the SVRNM partition boundary

This certification program contains several courses, each with its own software requirements. Refer to each of the course links provided in the course description and course contents for the specifics.